Resistive random access memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Fu Lee, Yu-Der Chih
Life of this patent
Estimating the term…
Abstract
A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.
Claims20
A memory device, comprising:
- a memory bit cell;
- a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current;
- and
- a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current,
- wherein when the read-out logic state is consistent with the first logic state, the control logic circuit is further configured to cease providing the first voltage to the memory bit cell,
- wherein when the read-out logic state is not consistent with the first logic state, the control logic circuit further causes the write circuit to use a second voltage to transition the memory bit cell still to the first logic state, and compare a second current flowing through the memory bit cell with a second reference current, and
- wherein the second voltage is higher than the first voltage, and the second reference current is higher than the first reference current.
A method, comprising:
- providing a first voltage to transition a memory bit cell to a first logic state;
- comparing a first current flowing through the memory bit cell with a first reference current;
- and
- monitoring the comparison between the first current and first reference current, wherein when the first current is lower than the first reference current, the method further comprises:
- providing a second voltage to transition the memory bit cell still to the first logic state;
- and
- comparing a second current flowing through the memory bit cell with a second reference current, wherein when a read-out logic state of the memory bit cell is consistent with the first logic state, the method further comprises ceasing providing the first voltage to the memory bit cell.
A method, comprising:
- providing a first voltage to transition a memory bit cell to a first logic state;
- comparing a first current corresponding to the first voltage and flowing through the memory bit cell with a first reference current;
- when the first current is higher than the first reference current, comparing a read-out logic state of the memory bit cell with the first logic state;
- when the read-out logic state is the same as the first logic state, ceasing to provide the first voltage to the memory bit cell;
- and
- when the read-out logic state is not the same as the first logic state, providing a second voltage to the memory bit cell.
Dependencies are inferred from the claim text.