Methods and apparatus for reading NAND flash memory
AssigneeNEO Semiconductor, Inc.
InventorFu-Chang Hsu
Life of this patent
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Abstract
Methods and apparatus for reading NAND flash memory are disclosed. In an embodiment, a method is provided for reading a NAND flash memory that includes strings of memory cells that are coupled to bit lines and word lines. The method includes precharging a plurality of bit lines to a precharge voltage level, and applying a sequence of word line voltages to a selected word line. The method also includes initiating discharge of one or more bit lines associated with one or more cells, respectively. The method also includes controlling discharging current of discharging bit lines to achieve identical discharge rates, waiting for a discharging time period for each bit line that is discharging, and latching bit line data at an end of each discharge time period.
Claims20
A method for reading a NAND flash memory, wherein the NAND flash memory comprises strings of memory cells that are coupled to bit lines and word lines, the method comprising:
- precharging a plurality of bit lines to a precharge voltage level;
- applying a sequence of word line voltages to a selected word line;
- initiating discharge of one or more bit lines associated with one or more cells, respectively, wherein discharge of a selected bit line is initiated when its associated cell is turned on when a selected word line voltage is higher than a threshold voltage (Vt) of the associated cell;
- controlling discharging current of discharging bit lines to achieve identical discharge rates;
- waiting for a discharging time period for each bit line that is discharging;
- and
- latching bit line data at an end of each discharge time period.
A NAND flash memory comprising:
- strings of memory cells that are coupled to bit lines and word lines;
- and
- a controller configured to perform operations of:
- precharging a plurality of the bit lines to a precharge voltage level;
- applying a sequence of word line voltages to a selected word line;
- initiating discharge of one or more bit lines associated with one or more cells, respectively, wherein discharge of a selected bit line is initiated when a cell associated with the bit line is turned on when a selected word line voltage is higher than a threshold voltage (Vt) of the associated cell;
- controlling discharging current of discharging bit lines to achieve identical discharge rates;
- waiting for a discharging time period for each bit line that is discharging;
- and
- latching bit line data at an end of each discharge time period.
A method for reading a NAND flash memory, wherein the NAND flash memory comprises strings of memory cells that are coupled to bit lines and word lines, the method comprising:
- precharging a plurality of bit lines to a precharge voltage level;
- applying a sequence of voltages on a selected word line to initiate discharging of one or more bit lines;
- controlling discharging current of discharging bit lines to achieve identical discharge rates;
- and
- latching bit line data of each discharging bit line at an end of a discharge time period.
Dependencies are inferred from the claim text.