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US 11,232,833 B2Granted
Dummy bitline circuitry
AssigneeArm Limited
InventorsAbhishek B. Akkur, Jitendra Dasani, Shri Sagar Dwivedi, Vivek Nautiyal, Satinderjit Singh, Vasimraja Bhavikatti
Life of this patent
Estimating the term…
Abstract
A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.
Claims26
A circuit comprising:
- a controller;
- a dummy wordline that is cut into a first part and a second part that is electrically isolated from the first part, wherein the first part is coupled to the controller, and wherein the second part is continuously electrically isolated from the controller;
- a dummy bitline coupled to the controller;
- a pMOSFET having a gate coupled to the first part of the dummy wordline, a source coupled to a supply rail, and a drain coupled to the dummy bitline;
- at least one dummy cell of a first type, each dummy cell of the first type comprising:
- a two transistor (2T) dummy cell;
- a single active pulldown nMOSFET having a gate coupled to the supply rail, a source coupled to ground, and a drain;
- and
- a first pass nMOSFET having a gate coupled to the first part of the dummy wordline, a source coupled to the drain of the active pulldown nMOSFET, and a drain coupled to the dummy bitline;
- and
- at least one dummy cell of a second type, each dummy cell of the second type comprising:
- a single dummy pulldown nMOSFET having a gate coupled the supply rail, a source coupled to ground, and a drain;
- and
- a second pass nMOSFET having a gate coupled to the second part of the dummy wordline, a source coupled to the drain of the dummy pulldown nMOSFET, and a drain coupled to the dummy bitline;
- a dummy wordline driver coupled to the first part of the dummy wordline between the controller and the gate of the pMOSFET, wherein the dummy wordline driver is also coupled to the first part of the dummy wordline between the controller and the gate of the pass nMOSFET of each dummy cell of the first type, and wherein the dummy wordline driver is electrically isolated from the second part of the dummy wordline;
- wherein the controller provides a sense amplifier enable (sae) signal to sense amplifier circuitry when the active pulldown nMOSFET de-asserts the dummy bitline.
13 more elements
A circuit comprising:
- a bitcell array including bitlines and wordlines;
- a dummy bitline that tracks the bitlines of the bitcell array;
- a dummy wordline that tracks the wordlines of the bitcell array, wherein the dummy wordline has a cut opening that electrically isolates a first part from a second part, and wherein the second part is coupled to ground;
- a two transistor (2T) dummy cell having a pass nMOSFET and a single active pulldown nMOSFET, wherein the pass nMOSFET has a gate coupled to the first part of the dummy wordline, a drain coupled to the dummy bitline, and a source, and wherein the active pulldown nMOSFET has a gate coupled to a supply rail, a source coupled to ground, and a drain coupled to the source of the pass nMOSFET;
- a pMOSFET having a gate coupled to the first part of the dummy wordline, a source coupled to the supply rail, and a drain coupled to the dummy bitline;
- a controller coupled to the dummy bitline and the first part of the dummy wordline, wherein the controller is electrically isolated from the second part of the dummy wordline, wherein the controller provides a sense amplifier enable (sae) signal to sense amplifier circuitry when the active pulldown nMOSFET de-asserts the dummy bitline;
- and
- a dummy wordline driver coupled to the first part of the dummy wordline between the controller and the gate of the pMOSFET, wherein the dummy wordline driver is also coupled to the first part of the dummy wordline between the controller and the gate of the pass nMOSFET, and wherein the dummy wordline driver is electrically isolated from the second part of the dummy wordline.
5 more elements
A circuit comprising:
- a dummy bitline;
- a dummy wordline having a first part and a second part that is electrically isolated from the first part;
- a pull-up transistor coupled between a supply rail and the dummy bitline, the pull-up transistor having a gate coupled to the first part of the dummy wordline;
- a first dummy cell having a first active pulldown transistor and a first pass transistor coupled in series between the dummy bitline and ground, the first active pulldown transistor having a gate coupled to the supply rail, and the first pass transistor having a gate coupled to the first part of the dummy wordline;
- a second dummy cell having a second active pulldown transistor and a second pass transistor coupled in series between the dummy bitline and ground, the second active pulldown transistor having a gate coupled to the supply rail, and the second pass transistor having a gate coupled to the second part of the dummy wordline;
- and
- a dummy wordline driver coupled to the first part of the dummy wordline, wherein the dummy wordline driver is electrically isolated from the second part of the dummy wordline.
4 more elements
Dependencies are inferred from the claim text.