US 11,232,828 B2Granted

Integrated memory assemblies comprising multiple memory array decks

AssigneeMicron Technology, Inc.

InventorsScott J. Derner, Charles L. Ingalls

Life of this patent

Estimating the term…

Loading patent…

Abstract

Some embodiments include an integrated memory assembly having a first memory array deck over a second memory array deck. A first series of conductive lines extends across the first memory array deck, and a second series of conductive lines extends across the second memory array deck. A first conductive line of the first series and a first conductive line of the second series are coupled with a first component through a first conductive path. A second conductive line of the first series and a second conductive line of the second series are coupled with a second component through a second conductive path. The first and second conductive lines of the first series extend through first isolation circuitry to the first and second conductive paths, respectively; and the first and second conductive lines of the second series extend through second isolation circuitry to the first and second conductive paths, respectively.

Claims19

Dependent claims

An integrated memory assembly, comprising:

a first memory tier over a second memory tier;
a first series of digitlines extending across the first memory tier, and a second series of digit lines extending across the second memory tier;
a first digit line of the first series and a first digit of the second series being coupled with a first sense amplifier through a first digit line path;
a second digit line of the first series and a second digit line of the second series being coupled with a second sense amplifier through a second digit line path;
the first and second digit lines of the first series extending through first isolation circuitry to the first and second digit line paths, respectively;
the first isolation circuitry including a first transistor which gatedly connects the first digit line of the first series to the first digit line path, and including a second transistor which gatedly connects the second digit line of the first series to the second digit line path;
the gates of the first and second transistors being coupled with a first isolation driver;
and
the first and second digit lines of the second series extending through second isolation circuitry to the first and second digit line paths, respectively;
the second isolation circuitry including a third transistor which gatedly connects the first digit line of the second series to the first digit line path, and including a fourth transistor which gatedly connects the second digit line of the second series to the second digit line path;
the gates of the third and fourth transistors being coupled with a second isolation driver.

8 more elements

An integrated memory assembly, comprising:

a first memory tier A over a second memory tier B;
a circuitry level below first memory tier A, the circuitry level comprising a first sense amplifier and a second sense amplifier;
a first series of digit lines along the first memory tier A, and including paired comparative digit lines BL-T-A1 and BL-C-A1, and paired comparative digit lines BL-T-A2 and BL-C-A2;
a second series of digit lines along the second memory tier B, and including paired comparative digit lines BL-T-B1 and BL-C-B1, and paired comparative digit lines BL-T-B2 and BL-C-B2;
the paired comparative digit lines BL-T-A1 and BL-C-A1 being coupled with the first sense amplifier through a first BL-T digit line path and a first BL-C digit line path, respectively;
the paired comparative digit lines BL-T-A2 and BL-C-A2 being coupled with the second sense amplifier through a second BL-T digit line path and a second BL-C digit line path, respectively;
the paired comparative digit lines BL-T-B1 and BL-C-B1 being coupled with the first sense amplifier through the first BL-T digit line path and the first BL-C digit line path, respectively;
the paired comparative digit lines BL-T-B2 and BL-C-B2 being coupled with the second sense amplifier through the second BL-T digit line path and the second BL-C digit line path, respectively;
and
the digit lines BL-T-A1, BL-C-A1, BL-T-A2 and BL-C-A2 extending through first isolation circuitry to the first BL-T digit line path, the first BL-C digit line path, the second BL-T digit line path and the second BL-C digit line path, respectively;
the first isolation circuitry comprising a multiplexer (MUX) and including a first transistor which gatedly connects BL-T-A1 to the first BL-T digit line path, a second transistor which gatedly connects BL-C-A1 to the first BL-C digit line path, a third transistor which gatedly connects BL-T-A2 to the second BL-T digit line path, and a fourth transistor which gatedly connects BL-C-A2 to the second BL-C digit line path;
the gates of the first, second, third and fourth second transistors being coupled with a first digit line isolation driver.

9 more elements

An integrated memory assembly, comprising:

a level of circuitry comprising first and second sense amplifiers;
a first memory array tier A over a second memory array tier B, the second memory tier B being elevationally over the level of circuitry;
a first series of wordlines along the first memory array tier A, and including wordlines WL-A1 and WL-A2;
a second series of wordlines along the second memory array tier B, and including wordlines WL-B1 and WL-B2;
the wordlines Wl-A1 and WL-B1 being coupled with a first wordline driver through a first wordline path;
the wordlines WL-A2 and WL-B2 being coupled with a second wordline driver through a second wordline path;
the wordlines WL-A1 and WL-A2 extending through first MUX isolation circuitry to the first and second conductive paths, respectively;
the first isolation circuitry including a first transistor which gatedly connects WL-A1 to the first wordline path, and including a second transistor which gatedly connects WL-A2 to the second wordline path;
the gates of the first and second transistors being coupled with a first wordline isolation driver;
and
the wordlines WL-B1 and WL-B2 extending through second MUX isolation circuitry to the first and second wordline paths, respectively;
the second isolation circuitry including a third transistor which gatedly connects WL-B1 to the first wordline path, and including a fourth transistor which gatedly connects of WL-B2 to the second wordline path;
the gates of the third and fourth transistors being coupled with a second wordline isolation driver.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/171,853Filed 9 Feb 2021 · continuation
Priority: 30 Jan 2017
Published: US 2021/0183428 A117 Jun 2021
Granted: 25 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

G11C 11/4085
Address circuits: word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 11/4097
Read-write [R-W] circuits: bit-line organisation, e.g. bit-line layout, folded bit lines

Family

Application62/452,193Us provisional application · filed 30 Jan 2017
Application15/797,462Parent of this continuation · filed 30 Oct 2017
Application16/503,356Parent of this continuation · filed 3 Jul 2019
US 10,366,738 B2Parent of this continuation · filed 30 Jul 2019
Application16/838,618Parent of this continuation · filed 2 Apr 2020
US 10,614,874 B2Parent of this continuation · filed 7 Apr 2020
US 2021/0183428 A1Pre-grant publication · published 17 Jun 2021
US 10,943,642 B2Parent of this continuation
US 2018/0218765 A1Published application
US 2019/0325940 A1Published application
US 2020/0234754 A1Published application
US 11,232,828 B2This patent

From the US filing history. Foreign family members aren’t listed.