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US 11,232,820 B2Granted
Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices
AssigneeSK hynix Inc.
InventorMin Su Park
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit is configured to generate an internal command pulse based on a write signal, a latency code, and an offset code. The sense data generation circuit is configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal.
Claims14
A semiconductor device comprising:
- an internal command pulse generation circuit configured to generate an internal command pulse based on a write signal, a latency code, and an offset code;
- and
- a sense data generation circuit configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal,
- wherein the delayed strobe signal is generated by delaying the internal data strobe signal;
- wherein the internal data strobe signal is generated by buffering a data strobe signal;
- and
- wherein the data strobe signal is generated to be delayed by a delay period which is controlled according to a logic level of the sense data.
4 more elements
A semiconductor system comprising:
- a controller configured to generate a control signal and a data strobe signal and configured to receive transmission data;
- and
- a semiconductor device configured to extract and store a latency code and an offset code from the control signal when a mode register write operation is performed, configured to generate an internal command pulse based on a write signal, the latency code, and the offset code, and configured to generate the transmission data based on the internal command pulse and the data strobe signal;
- wherein the semiconductor device includes a command decoder configured to decode an internal control signal generated by buffering the control signal to generate a mode register write signal and the write signal;
- and
- wherein the mode register write signal is generated to perform the mode register write operation, and the write signal is generated to perform a write operation.
3 more elements
Dependencies are inferred from the claim text.