Shift register and driving method for compensating for linear pattern appearing on display device

A shift register comprising a compensation selection circuit, a storage circuit, a blanking input circuit, and a shift register circuit,

• wherein the compensation selection circuit is coupled to a compensation selection control signal terminal, an input terminal, and a first node, and is configured to provide an input signal from the input terminal to the first node according to a compensation selection control signal from the compensation selection control signal terminal;
• wherein the storage circuit is coupled to a blanking control signal terminal and the first node, and is configured to store and maintain a voltage difference between the blanking control signal terminal and the first node;
• wherein the blanking input circuit is coupled to the first node, a blanking input signal terminal, and a second node, and is configured to provide a blanking input signal from the blanking input signal terminal to the second node according to a voltage of the first node;
• and
• wherein the shift register circuit is coupled to the second node, a clock signal terminal, the input terminal, and an output terminal, and is configured to provide, during a blanking period, a compensation driving signal via the output terminal according to a voltage of the second node and a clock signal from the clock signal terminal, and provide, during a display period, a scan driving signal via the output terminal according to the input signal and the clock signal,
• wherein the shift register circuit comprises a display input circuit, an output circuit, a pull-down circuit, a pull-down control circuit, a display reset circuit, and a blanking reset circuit;
• wherein the display input circuit is coupled to the input terminal and the second node, and is configured to provide the input signal to the second node;
• wherein the output circuit is coupled to the second node, the clock signal terminal, and the output terminal, and is configured to output, during the display period, the scan driving signal according to the voltage of the second node and the clock signal, and output, during the blanking period, the compensation driving signal according to the voltage of the second node and the clock signal;
• wherein the pull-down circuit is coupled to the second node, a third node, a first voltage terminal, and the output terminal, and is configured to control voltages of the second node and the output terminal according to a voltage of the third node;
• wherein the pull-down control circuit is coupled to the second node and the third node, and is configured to control the voltage of the third node according to the voltage of the second node;
• wherein the display reset circuit is coupled to a display reset signal terminal, the second node, and the first voltage terminal, and is configured to reset the voltage of the second node according to a display reset signal from the display reset signal terminal;
• and
• wherein the blanking reset circuit is coupled to the blanking reset signal terminal, the second node, and the first voltage terminal, and is configured to reset the voltage of the second node according to a blanking reset signal from the blanking reset signal terminal.