Shift register unit, driving method, gate driving circuit and display device

A shift register unit, comprising:

• a first gate driving output circuit;
• and
• a second gate driving output circuit,
• wherein the first gate driving output circuit is configured to output a first gate driving signal through a first gate driving signal output terminal,
• wherein the second gate driving output circuit is configured to generate a second gate driving signal based on the first gate driving signal, a first clock signal, and a second clock signal,
• wherein the first gate driving output circuit is used to control to output the first gate driving signal under the control of the third clock signal and the fourth clock signal,
• wherein the first pull-down node control circuit includes a first pull-down node control transistor, a second pull-down node control transistor, a first pull-down node control capacitor, and a second pull-down node control capacitor, and the pull-down circuit includes a pull-down transistor,
• wherein a control electrode of the first pull-down node control transistor is electrically connected to the first gate driving signal output terminal, and a first electrode of the first pull-down node control transistor is electrically connected to the first voltage terminal, and a second electrode of the first pull-down node control transistor is electrically connected to the first pull-down node,
• wherein a control electrode of the second pull-down node control transistor is electrically connected to the first clock signal terminal, a first electrode of the second pull-down node control transistor is electrically connected to the first pull-down node, and a second electrode of the second pull-down node control transistor is electrically connected to the third voltage terminal,
• wherein a first end of the first pull-down node control capacitor is electrically connected to the first pull-down node, and a second end of the first pull-down node control capacitor is electrically connected to the second clock signal terminal,
• wherein a first end of the second pull-down node control capacitor is electrically connected to the first pull-down node, and a second end of the second pull-down node control capacitor is connected to the second gate driving signal output terminal, and
• wherein a control electrode of the pull-down transistor is electrically connected to the first pull-down node, a first electrode of the pull-down transistor is electrically connected to the second gate driving signal output terminal, and a second electrode of the pull-down transistor is electrically connected to the second voltage terminal.

A driving method applied to a shift register unit, wherein the shift register unit comprises a first gate driving output circuit and a second gate driving output circuit,

• wherein the first gate driving output circuit is configured to output a first gate driving signal through a first gate driving signal output terminal,
• wherein the second gate driving output circuit is configured to generate a second gate driving signal based on the first gate driving signal, a first clock signal, and a second clock signal,
• wherein the second gate driving circuit comprises a first pull-down node control circuit, a pull-down circuit, and an output control circuit, and
• wherein the output control circuit is used to control connection or disconnection between a second gate driving signal output terminal and a first voltage terminal under the control of the first gate driving signal,
• wherein the driving method comprises:
• in an output phase, the first gate driving output circuit outputting the first level;
• the potential of the first clock signal being the second level, the potential of the second clock signal being the first level, and the second gate driving output circuit controlling the potential of the second gate driving signal to be the second level under the control of the first gate driving signal;
• in a reset phase, the first gate driving output circuit outputting the second level, the potential of the first clock signal being the first level, the potential of the second clock signal being the second level, and the second gate driving output circuit controlling the potential of the second gate driving signal to be the first level under the control of the first clock signal;
• and
• in an output cut-off maintenance phase, the first gate driving output circuit outputting the second level, and the second gate driving output circuit controlling the potential of the second gate driving signal to be the first level under the control of the first clock signal and the second clock signal.