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US 11,232,726 B2Granted
Semiconductor integrated circuit
AssigneeRohm Co., Ltd.
InventorNorikazu Murakami
Life of this patent
Estimating the term…
Abstract
An asynchronous FIFO is arranged between an input bus and an output bus with a different number of lanes. The asynchronous FIFO supplies a write clock and a read clock. A circuit block receives output data from the asynchronous FIFO via the output bus, and executes predetermined processing. In a test mode, a test circuit supplies a test pattern as interrupt data to the input bus, and detects the presence or absence of an abnormality based on a relation between the output data and its expected value based on the test pattern.
Claims15
A semiconductor integrated circuit comprising:
- a PLL (Phase-Locked Loop) circuit structured to frequency multiply a write clock so as to generate a read clock;
- an asynchronous FIFO (First In First Out) arranged between an input bus and an output bus configured with a different number of lanes;
- a circuit block structured to receive output data of the asynchronous FIFO via the output bus, and to execute predetermined processing;
- and
- a test circuit structured to, in a test mode, supply a test pattern as interrupt data to the input bus, and to detect an abnormality based on a relation between the output data and an expected value based on the test pattern.
2 more elements
A bridge chip comprising:
- a receiver structured to receive image data from an external processor;
- a processing unit structured to process the image data received by the receiver;
- a PLL (Phase-Locked Loop) circuit structured to frequency multiply a write clock so as to generate a read clock;
- an asynchronous FIFO (First In First Out) to which the image data processed by the processing unit is to be written according to the write clock, and from which the image data can be read out according to the read clock;
- a transmitter structured to transmit output data of the asynchronous FIFO to an external circuit;
- and
- a test circuit structured to, in a test mode, supply a test pattern as interrupt data to a data input terminal of the asynchronous FIFO, and to detect an abnormality based on a relation between the output data and an expected value based on the test pattern.
4 more elements
Dependencies are inferred from the claim text.