Data structure descriptors for deep learning acceleration

A system comprising:

• a plurality of processing elements, each processing element comprising a fabric router coupled to a compute element;
• wherein each processing element is enabled to selectively communicate fabric packets with others of the processing elements at least in part via the fabric router of the respective processing element;
• and
• wherein each compute element comprises a memory and is enabled to
• decode an instruction comprising an operand field,
• access an operand descriptor based at least in part on the operand field,
• decode the operand descriptor to determine a particular one of a plurality of mutually exclusive types the operand descriptor refers to, the mutually exclusive types comprising a fabric type and a memory type,
• access an operand in accordance with the operand descriptor and the particular type,
• wherein the access of the operand is via the respective fabric router coupled to the compute element responsive to the particular type being the fabric type, and
• wherein the access of the operand is via the memory responsive to the particulate type being the memory type.

A system comprising:

• means for decoding an instruction, the instruction comprising an operand field;
• means for accessing an operand descriptor based at least in part on the operand field;
• means for decoding the operand descriptor to determine a particular one of a plurality of mutually exclusive types the operand descriptor refers to;
• means for accessing an operand in accordance with the operand descriptor and the particular type;
• means for performing an iteration of the instruction via accessing, in accordance with an access pattern described by the operand descriptor, sufficient data elements of a vector for the iteration;
• wherein the mutually exclusive types comprise a fabric type and a memory type;
• wherein a compute element comprises the means for decoding an instruction, the means for accessing an operand descriptor, the means for decoding the operand descriptor, the means for accessing an operand, and the means for performing an iteration;
• wherein the compute element is comprised in a processing element that comprises a fabric router, and the processing element is one of a plurality of processing elements each comprising a respective compute element and a respective fabric router;
• wherein the processing elements are interconnected via a fabric coupled to the respective fabric routers;
• wherein responsive to the particular type being the fabric type, the operand is accessed via the fabric;
• and
• wherein responsive to the particular type being the memory type, the operand is accessed via a memory of the compute element.