Routing-resource-improving method of generating layout diagram and system for same

A system for manufacturing a semiconductor device, the system comprising:

• at least one processor;
• and
• at least one memory including computer program code for one or more programs;
• wherein the at least one memory, the computer program code and the at least one processor are configured to cause the system to execute:
• for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including first and overlying second levels (corresponding M_1st and M_2nd levels) of metallization and a first level (VIA_1st level) of interconnection therebetween corresponding to first and overlying second layers of metallization and a first layer of interconnection therebetween in the semiconductor device,
• generating the layout diagram including:
• selecting a candidate pattern in the layout diagram, the candidate pattern being a first conductive pattern in the M_2nd level (first M_2nd pattern) or a first conductive pattern in the M_1st level (first M_1st pattern);
• determining that the candidate pattern satisfies one or more criteria including at least one criterion regarding a pre-existing via pattern in the layout diagram;
• and
• changing a size of the candidate pattern thereby revising the layout diagram;
• and
• wherein:
• the layout diagram further includes a transistor level corresponding to a transistor layer in the semiconductor device;
• and
• there are no levels of metallization between the M_1st level and the transistor layer.

A method of manufacturing a semiconductor device, the method comprising:

• for a layout diagram stored on a non-transitory computer-readable medium, the semiconductor device being based on the layout diagram, the layout diagram including first and overlying second levels (corresponding M_1st and M_2nd levels) of metallization and a first level (VIA_1st level) of interconnection therebetween corresponding to first and overlying second layers of metallization and a first layer of interconnection therebetween in the semiconductor device,
• generating the layout diagram including:
• selecting a first conductive pattern in the M_2nd level (first M_2nd pattern) of the layout diagram as a candidate pattern;
• determining criteria-satisfaction by the candidate pattern of one or more criteria including at least one criterion regarding a pre-existing via pattern in the layout diagram, the determining criteria-satisfaction including:
• determining that the first M_2nd pattern is designated as a pin pattern;
• determining that a first via pattern in the VIA 1st level (first VIA_1st pattern) of interconnection is a sole VIA_1st pattern which is overlapped by the first M_2nd pattern;
• and
• removing the first M_2nd pattern from the layout diagram thereby revising the layout diagram.