Computer system and device management method
AssigneeHitachi, Ltd.
InventorsNaoya Okamura, Takumi Tsujishita, Masanori Fujii
Life of this patent
Estimating the term…
Abstract
In a storage system including an FPGA having a logic which executes a prescribed processing and a plurality of devices coupled to the FPGA via a bus, the logic of the FPGA is configured to: attempt to access the plurality of devices and, based on a status of access to the devices, determine whether or not there is an abnormality in the access to the devices; and when it is determined that there is an abnormality in the access to a device, reset an IF unit for performing a communication processing via a bus of the device.
Claims6
A computer system, comprising:
- a first controller having a first central processing unit (CPU), a first main storage unit and a first relay having a first interface unit;
- a second controller having a second CPU, a second main storage unit and a second relay which is coupled to the first relay of the first controller via a communication path;
- a processing unit of the first controller having a hardware logic configured to execute prescribed processing;
- and
- a plurality of devices of the first controller coupled to the processing unit via a bus,
- wherein the hardware logic of the processing unit is configured to:
- attempt to access each of the plurality of devices,
- upon determining access to a device, among the plurality of devices, has timed out, determine whether the device or the bus cause a deadlock in the first controller, attempt to access the second main storage unit of the second controller and upon determining access to the second main storage unit is unresponsive, and output a signal to reset the first interface unit of the first relay to disconnect the communication path coupling the first controller to the second controller, and
- wherein the first CPU and the second CPU are each configured to detect whether the communication path has been disconnected and upon determining the communication path has been disconnected, at least the second CPU blocks the first controller.
A device management method by a computer system including a first controller having a first central processing unit (CPU), a first main storage unit and a first relay having a first interface unit;
- a second controller having a second CPU, a second main storage unit and a second relay which is coupled to the first relay of the first controller via a communication path;
- a processing unit of the first controller having a hardware logic that executes prescribed processing;
- and a plurality of devices of the first controller coupled to the processing unit via a bus, the device management method comprising:
- attempting, by the hardware logic of the processing unit, to access each of the plurality of devices;
- upon determining access to a device, among the plurality of devices, has timed out, determine whether the device or the bus cause a deadlock in the first controller, attempt to access the second main storage unit of the second controller and upon determining access to the second main storage unit is unresponsive, and output a signal to reset the first interface unit of the first relay to disconnect the communication path coupling the first controller to the second controller,
- wherein the first CPU and the second CPU are each configured to detect whether the communication path has been disconnected and upon determining the communication path has been disconnected, at least the second CPU blocks the first controller.
Dependencies are inferred from the claim text.