Dedicated cache-related block transfer in a memory system
AssigneeRambus Inc.
InventorLiji Gopalakrishnan
Life of this patent
Estimating the term…
Abstract
A memory system includes a dynamic random access memory (DRAM) device, a second memory device, and a memory controller circuit. The memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the memory controller circuit and the DRAM device on behalf of a host, and is also coupled to the DRAM device by a second data channel configured to transfer second data between the memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data channel.
Claims20
A system comprising:
- a dynamic random access memory (DRAM) device;
- a second memory device;
- and
- a first memory controller circuit, wherein the first memory controller circuit is coupled to the DRAM device by a first data channel configured to transfer first data between the first memory controller circuit and the DRAM device on behalf of a host, and wherein the first memory controller circuit is coupled to the DRAM device by a second data channel configured to transfer second data between the first memory controller circuit and the DRAM device on behalf of the second memory device while the first data is being transferred across the first data channel.
A device comprising:
- a first memory;
- a second memory;
- and
- a controller coupled to the first memory and to the second memory, wherein the controller is configured to:
- perform a first data transfer operation for first data between the controller and a first portion of the first memory using a first data channel;
- and
- perform, concurrently with the first data transfer operation, a second data transfer operation for second data between the controller and a second portion of the first memory using a second data channel, wherein the second portion of the first memory serves as a cache for the second memory.
A memory device comprising:
- a first port to couple the memory device to a memory controller, the first port to transfer first data between the memory device and the memory controller in response to a host data access request;
- and
- a second port to couple the memory device to the memory controller, the second port to transfer second data between the memory device and the memory controller in response to a cache management operation associated with a separate memory device, wherein the transfer of the second data via the second port at least partially overlaps in time with the transfer of the first data via the first port.
Dependencies are inferred from the claim text.