US 11,232,042 B2Granted

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system

AssigneeMicrosoft Technology Licensing, LLC

InventorsMadhavan Thirukkurungudi Venkataraman, Thomas Philip Speier

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Abstract

Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Claims28

Dependent claims

A memory management system in a central processing unit (CPU) in a processor of a processor-based system, comprising:

a page table in a system memory of the processor-based system, the page table comprising a plurality of level page tables each comprising a plurality of page table entries that are addressable by a different level index of a virtual address (VA) and the plurality of page table entries configured to store a physical address (PA) associated with the VA;
a memory management unit (MMU) translation lookaside buffer (TLB) comprising a plurality of MMU TLB entries each configured to store a cached page table entry of the plurality of page table entries;
an in-memory TLB in the system memory, the in-memory TLB comprising a plurality of in-memory TLB entries each configured to store a cached page table entry of the plurality of page table entries;
a page table walker circuit configured to access the plurality of page table entries in the plurality of level page tables in the page table based on the VA;
and an MMU circuit configured to:
receive a memory access request comprising a request VA based on a computer software instruction executed for a process in the CPU;
determine if an MMU TLB entry, among the plurality of MMU TLB entries in the MMU TLB, contains a page table entry comprising a PA corresponding to the request VA;
and in response to determining the MMU TLB does not contain the MMU TLB entry containing the page table entry comprising the PA corresponding to the request VA:
determine if a VA stored in a first in-memory TLB entry, among the plurality of in-memory TLB entries in the in-memory TLB allocated to the process in the CPU, matches the request VA;
in response to determining the VA stored in the first in-memory TLB entry matches the request VA, translate the request VA to a PA based on the first in-memory TLB entry;
and in response to determining the VA stored in the first in-memory TLB entry does not match the request VA, cause the page table walker circuit to:
access the plurality of level page tables in the page table based on the request VA;
translate the request VA to a first PA contained in a first page table entry in the plurality of level page tables corresponding to the request VA;
write the first page table entry, in at least one level page table of the plurality of level page tables in the page table corresponding to the request VA, to a first MMU TLB entry in the MMU TLB;
and in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB:
in response to the first page table entry in the at least one level page table being in a highest level page table of the plurality of level page tables:
not write the first page table entry to an in-memory TLB entry in the in-memory TLB.

14 more elements

A method of translating a virtual address (VA) to a physical address (PA) in a central processing unit (CPU) in a processor of a processor-based system, comprising:

receiving a memory access request comprising a request VA based on a computer software instruction executed for a process in the CPU;
determining a memory management unit (MMU) translation lookaside buffer (TLB) entry, in an MMU TLB comprising a plurality of MMU TLB entries each configured to store a cached page table entry of a plurality of page table entries, does not contain a page table entry comprising a PA corresponding to the request VA,
wherein the page table entry is contained in a page table comprising a plurality of level page tables each comprising a plurality of page table entries that are addressable by a VA and the plurality of page table entries configured to store a PA associated with the VA;
and in response to determining the MMU TLB does not contain the MMU TLB entry containing the page table entry comprising the PA corresponding to the request VA:
determining a VA stored in a first in-memory TLB entry, among a plurality of in-memory TLB entries in the in-memory TLB in the system memory of the processor-based system that is allocated to the process in the system memory in the processor-based system, does not match the request VA;
in response to determining the VA stored in the first in-memory TLB entry matches the request VA, translating the request VA to a PA based on the first in-memory TLB entry;
and in response to determining the VA stored in the first in-memory TLB entry does not match the request VA, cause a page table walker circuit to:
access at least one level page table in the plurality of level page tables based on the request VA;
translate the request VA to a first PA contained in a first page table entry in the plurality of level page tables corresponding to the request VA;
write the first page table entry, in the plurality of level page tables in the page table corresponding to the request VA, to a first MMU TLB entry in the MMU TLB;
and in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB:
in response to the first page table entry in the plurality of level page tables being in a highest level page table of the plurality of level page tables:
not write the first page table entry to an in-memory TLB entry in the in-memory TLB.

10 more elements

A processor-based system, comprising:

a system memory;
a processor comprising one or more central processing units (CPUs) each configured to execute computer instructions in an operating system software program and one or more processes;
a memory management system, in a CPU of the one or more CPUs, comprising:
a page table in the system memory, the page table comprising a plurality of level page tables each comprising a plurality of page table entries that are addressable by a different level index of a virtual address (VA) and the plurality of page table entries configured to store a physical address (PA) associated with the VA;
a memory management unit (MMU) translation lookaside buffer (TLB) comprising a plurality of MMU TLB entries each configured to store a cached page table entry of the plurality of page table entries;
an in-memory TLB in the system memory, the in-memory TLB comprising a plurality of in-memory TLB entries each configured to store a cached page table entry of the plurality of page table entries;
a page table walker circuit configured to access a page table entry in the plurality of level page tables in the page table based on the VA;
and an MMU circuit configured to:
receive a memory access request comprising a request VA based on a computer software instruction executed for a process among the one or more processes in a CPU among the one or more CPUs;
determine if an MMU TLB entry in the MMU TLB contains a page table entry comprising a PA corresponding to the request VA;
in response to determining the MMU TLB does not contain the MMU TLB entry containing the page table entry comprising the PA corresponding to the request VA:
determine if a VA stored in a first in-memory TLB entry, in the in-memory TLB allocated to the process in the system memory in the processor-based system, matches the request VA;
and in response to determining the VA stored in the first in-memory TLB entry matches the request VA, translate the request VA to a PA based on the first in-memory TLB entry;
and in response to determining the VA stored in the first in-memory TLB entry does not match the request VA, cause the page table walker circuit to:
access the plurality of level page tables in the page table based on the request VA;
translate the request VA to a first PA contained in a first page table entry in one level page table of the plurality of level page tables corresponding to the request VA;
write the first page table entry, in the one level page table of the plurality of level page tables in the page table corresponding to the request VA, to a first MMU TLB entry in the MMU TLB;
and in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB:
in response to the first page table entry in the one level page table being in a highest level page table of the plurality of level page tables:
not write the first page table entry to an in-memory TLB entry in the in-memory TLB.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/685,320Filed 15 Nov 2019
Published: US 2021/0149818 A120 May 2021
Granted: 25 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 12/1027
Address translation: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
G06F 12/1036
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: for multiple virtual address spaces,…
G06F 2212/651
Details of virtual memory and virtual address translation: multi-level translation tables