Memory controller with pre-loader
AssigneeIntel Corporation
InventorsFrancesc Guim Bernat, Kshitij Doshi
Life of this patent
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Abstract
Embodiments of the present disclosure relate to a controller that includes a monitor to determine an access pattern for a range of memory of a first computer memory device, and a pre-loader to pre-load a second computer memory device with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the subset includes a plurality of cache lines. In some embodiments, the controller includes a specifier and the monitor determines the access pattern based at least in part on one or more configuration elements in the specifier. Other embodiments may be described and/or claimed.
Claims20
An apparatus comprising:
- a monitor to determine an access pattern for a range of memory of a first tier of memory of a computer system;
- and
- a pre-loader to pre-load a second tier of memory of the computer system with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the second tier of memory is nearer to a processor of the computer system with respect to access latency than the first tier of memory, wherein the processor is associated with a cache line length and the subset of the range of memory has a length that corresponds to a plurality of the cache line lengths.
A method, comprising:
- determining an access pattern for a range of memory of a first tier of memory of a computer system;
- and
- pre-loading a second tier of memory of the computer system with a copy of a subset of the range of memory based at least in part on the access pattern, wherein the second tier of memory is nearer to a processor of the computer system with respect to access latency than the first tier of memory, wherein the processor is associated with a cache line length and the subset of the range of memory has a length that corresponds to a plurality of the cache line lengths.
A computer system comprising:
- a processor;
- a memory device coupled with the processor;
- and
- a network interface coupled with the memory device, wherein the network interface includes:
- a monitor to determine an access pattern for a range of memory of a remote memory device over a network fabric by the processor, and
- a pre-loader to pre-load the memory device with a copy of a subset of the range of memory based at least in part on the determined access pattern, wherein the processor is associated with a cache line length and the subset of the range of memory has a length that corresponds to a plurality of the cache line lengths.
Dependencies are inferred from the claim text.