Method to enable the prevention of cache thrashing on memory management unit (MMU)-less hypervisor systems
AssigneeInfineon Technologies AG
InventorsManoj Kumar Harihar, Romain Ygnace
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AssigneeInfineon Technologies AG
InventorsManoj Kumar Harihar, Romain Ygnace
Estimating the term…
A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.
A cache circuit associated with a hypervisor system, comprising:
A hypervisor system, comprising:
A method for a cache circuit associated with a hypervisor system, comprising:
Dependencies are inferred from the claim text.