Debug for computation networks using error detection codes

A neural network processor comprising:

• a processing engine configured to execute instructions to implement multiple layers of a neural network and to generate output data based on input data to the processing engine;
• a debugging circuit physically distinct from and coupled to the processing engine, the debugging circuit configured to generate error detection codes for the input data to the processing engine or error detection codes for the output data generated by the processing engine, wherein the debugging circuit is further configured to determine a debug level at which to operate, and wherein the debugging circuit can operate at different debug levels, the different debug levels including a first debug level settable to cause error detection code generation at a start of an individual instruction executed by the processing engine and a second debug level settable to cause error detection code generation at an end of the individual instruction;
• and
• an interface to a memory device, wherein the interface is configured to save the error detection codes generated by the debugging circuit into the memory device.

A computer-implemented method, comprising:

• receiving, at a processing engine of a neural network processor for implementing multiple layers of a neural network, input data for a first instruction to be executed by the processing engine;
• executing, by the processing engine, the first instruction to generate output data based on the input data;
• determining, by a debugging circuit of the neural network processor, a debug level at which to operate, wherein the debugging circuit can operate at different debug levels, the different debug levels including a first debug level settable to cause error detection code generation at a start of the first instruction and a second debug level settable to cause error detection code generation at an end of the first instruction;
• after determining the debug level at which to operate, generating, by the debugging circuit, one or more error detection codes for the first instruction based on at least one of the input data or the output data and according to the debug level at which to operate, wherein the debugging circuit is physically distinct from and coupled to the processing engine;
• and
• saving, through an interface between the debugging circuit and a memory device, the one or more error detection codes in the memory device.