Semiconductor memory devices, memory systems including the same and methods of operating memory systems

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device includes:
• a memory cell array including a plurality of memory bank arrays, wherein each memory bank array includes a plurality of memory cell rows, wherein each of the memory cell rows includes a plurality of sub-pages to store a plurality of codewords, each codeword including a main data and a parity data associated with the main data;
• an error correction circuit;
• an error log register;
• and
• a control logic circuit configured to control the error correction circuit to perform an error correction code (ECC) decoding sequentially on the sub-pages for detecting at least one bit error in each of the memory cell rows in response to a first command from the memory controller in an error check and scrub (ECS) mode, wherein the control logic circuit is configured to perform an error logging operation to write error information into the error log register, and
• wherein the error information includes a number of faulty codewords in each of some faulty memory cell rows, which is determined by the control logic circuit, wherein the at least one bit error is detected in each of the at faulty codewords, wherein the semiconductor memory device is configured to notify the memory controller that the number of error occurrences in one memory cell row of the some faulty memory cell rows has reached a threshold immediately by using an alert signal, and wherein the memory controller is configured to apply a scrubbing command to the semiconductor memory device, in response to the alert signal.

A method of operating a memory system including a semiconductor memory device and a memory controller configured to control the semiconductor memory device, wherein the semiconductor memory device includes a memory cell array including a plurality of memory bank arrays, each memory bank array includes a plurality of memory cell rows, each of the memory cell rows includes a plurality of sub-pages to store a plurality of codewords, and each codeword includes a main data and a parity data associated with the main data, the method comprising:

• generating, by the memory controller, a first command and an access address;
• performing, by an error correction circuit in the semiconductor memory device, an error correction code (ECC) decoding sequentially on the sub-pages for detecting at least one bit error in each of the sub-pages, in response to the first command in an ECS mode;
• performing, by a control logic circuit in the semiconductor memory device, an error logging operation to write error information into an error log register, the error information including a number of faulty codewords in each of some faulty memory cell rows;
• transmitting, by the semiconductor memory device, the page error information as an error information signal to the memory controller;
• notifying, by the semiconductor memory device, the memory controller that the number of error occurrences in one memory cell row of the some faulty memory cell rows has reached a threshold immediately by using an alert signal;
• and
• applying, by the memory controller, a scrubbing command to the semiconductor memory device, in response to the alert signal.