System on chip and memory system including security processor with improved memory use efficiency and method of operating system on chip

A method of operating a system on chip, the method comprising:

• receiving data and a first address corresponding to the data;
• generating encrypted data by performing an encryption operation on the data by using Metadata, the first address being associated with a first region of a single standalone memory unit for storing the encrypted data;
• generating error correction code (ECC) data by performing ECC encoding processing on the encrypted data and the Metadata;
• and generating a second address that represents positions in which the Metadata and the ECC data are stored in a second region of the single standalone memory unit based on the first address and a size of the Metadata and the ECC data, the second address being associated with the second region of the single standalone memory unit for storing the Metadata and the ECC data, and wherein the second address comprises information by which at least some of the Metadata and the ECC data are stored in a same row or in a same column in the single standalone memory unit.

A memory system, comprising:

• a memory controller that is configured to communicate with a memory, wherein the memory controller comprises:
• an encryption/ECC encoding processor configured to perform an encryption operation on data by using Metadata and to generate ECC data by performing ECC encoding processing on encrypted data and the Metadata;
• a decryption/ECC decoding processor configured to extract the encrypted data and the Metadata by performing ECC decoding processing by using the ECC data and to recover the data by performing a decryption operation on the encrypted data by using the Metadata;
• an address controller configured to receive a first address related to storage of the encrypted data in a first region of a single standalone memory unit, to generate a second address based on the first address and a size of the Metadata and the ECC data, and to indicate a second region of the single standalone memory unit for storing the Metadata and the ECC data based on the generated second address;
• and an interface circuit configured to interface with the single standalone memory unit for data access based on the first and second addresses.