System and method for controlling the order of instruction execution by a target device
AssigneeSamsung Electronics Co., Ltd.
InventorsRichard N. Deglin, Yash Jajoo, Vulligadla Amaresh, Jihyun Kim
Life of this patent
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Abstract
A system and method for executing instructions in a constrained order. In some embodiments, the method includes: sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction; receiving, by a target, the first instructions, the order-constrained instruction, and the second instruction; and executing, by the target, the first instruction; the order-constrained instruction, after executing the first instruction; and the second instruction, after executing the order-constrained instruction.
Claims20
A method for executing instructions in a constrained order, the method comprising:
- sending by a host, a first instruction, followed by an order-constrained instruction, followed by a second instruction;
- receiving, by a target, the first instruction, the order-constrained instruction, and the second instruction;
- and
- executing, by the target,
- the first instruction;
- the order-constrained instruction, after executing the first instruction;
- and
- the second instruction, after executing the order-constrained instruction,
- wherein the executing, by the target, the first instruction, the order-constrained instruction, and the second instruction comprises:
- entering the first instruction in an instruction ordering;
- transmitting an acknowledgment to the host indicating the first instruction is entered or to be entered in the instruction ordering;
- receiving, from the host, the order-constrained instruction in response to the acknowledgment;
- and
- entering the order-constrained instruction in the instruction ordering in an order after the first instruction, and
- wherein the target is configured to execute the first instruction and the order-constrained instruction in the same order as the instruction ordering.
A system comprising a target,
- the target comprising a processing circuit,
- the processing circuit being configured to:
- receive a first instruction;
- send an acknowledgment for the first instruction;
- execute the first instruction;
- receive a second instruction;
- send an acknowledgment for the second instruction;
- and
- execute the second instruction,
- wherein
- the executing of the first instruction and
- the executing of the second instruction
- are performed in the same order as
- the sending of the acknowledgment for the first instruction and
- the sending of the acknowledgment for the second instruction, and
- wherein the executing of the first instruction and the second instruction comprises:
- entering the first instruction and the second instruction in an instruction ordering in an order in which the first instruction and the second instruction are received;
- sending the acknowledgements for the first and second instructions in response to the entering of the first and second instructions in the instruction ordering;
- and
- executing the first instruction and the second instruction in the same order as the instruction ordering.
A system comprising a target,
- the target comprising means for processing,
- the means for processing being configured to:
- receive a first instruction;
- send an acknowledgment for the first instruction;
- execute the first instruction;
- receive a second instruction;
- send an acknowledgment for the second instruction;
- and
- execute the second instruction,
- wherein
- the executing of the first instruction and
- the executing of the second instruction
- are performed in the same order as
- the sending of the acknowledgment for the first instruction and
- the sending of the acknowledgment for the second instruction, and
- wherein the executing of the first instruction and the second instruction comprises:
- entering the first instruction and the second instruction in an instruction ordering in an order in which the first instruction and the second instruction are received;
- sending the acknowledgements for the first and second instructions in response to the entering of the first and second instructions in the instruction ordering;
- and
- executing the first instruction and the second instruction in the same order as the instruction ordering.
Dependencies are inferred from the claim text.