Mechanism for mitigating information leak via cache side channels during speculative execution
AssigneeAdvanced Micro Devices, Inc.
InventorSooraj Puthoor
Life of this patent
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Abstract
A processor includes a first core and a second core to execute computer instructions. Each of the cores includes its own private memory cache and speculative load queue. The speculative load queue stores cachelines for the computer instructions and data when the core is operating in a speculative state with respect to a process or thread. The processor includes a state tracking buffer having a state field to store a speculative exclusive ownership state for each cacheline in the speculative load queue when present therein.
Claims20
A processor comprising:
- a first core to execute computer instructions;
- a first private memory cache coupled to the first core;
- a speculative load queue coupled to the first core, the speculative load queue to store a plurality of cachelines for computer instructions executed speculatively at the first core, each cacheline of the plurality of cachelines storing a plurality of instructions;
- and
- a state tracking buffer having a state field to store a state for each cacheline of the plurality of cachelines in the speculative load queue, the state tracking buffer having a speculative execution state associated with a corresponding cacheline in the state tracking buffer, the speculative execution state signaling the processor to execute the computer instructions from the speculative load queue when the first core is in a speculative execution mode.
A method for speculative execution in a directory-based cache coherence system, the method comprising:
- receiving a load speculative request to a local private L1 memory cache of a first processor core for a cacheline;
- for a local L1 memory cache miss:
- creating an entry into a speculative load queue for the cacheline;
- forwarding the load speculative request to a cacheline of a local private L1 memory cache of a second processor core;
- issuing data according to the load speculative request;
- determining whether the cacheline of the L1 memory cache of the second processor core is in a modified (M) state or a speculative-modified (MSPEC) state, the MSPEC state indicating that the directory-based cache coherence system is to execute the cacheline from the speculative load queue, and the M state indicating that the directory-based cache coherence system is to execute the cacheline from the L1 memory cache;
- changing the M state to the MSPEC state when the cacheline of the L1 memory cache is in the M state;
- and
- providing data according to the load speculative request to a load queue of the first processor core when the cacheline of the L1 memory cache is in the MSPEC state.
A non-transitory computer readable storage medium including instructions stored thereon, which when executed by a processor, cause the processor to perform operations comprising:
- receiving a load speculative request to a local private L1 memory cache of a first processor core for a cacheline;
- for a local L1 memory cache miss:
- creating an entry into a speculative load queue for the cacheline;
- forwarding the load speculative request to a cacheline of a local private L1 memory cache of a second processor core;
- issuing data according to the load speculative request;
- determining whether the cacheline of the L1 memory cache of the second processor core is in a modified (M) state or a speculative-modified (MSPEC) state, the MSPEC state indicating that the processor is to execute the cacheline from the speculative load queue, and the M state indicating that the processor is to execute the cacheline from the L1 memory cache;
- changing the M state to the MSPEC state when the cacheline of the L1 memory cache is in the M state;
- and
- providing data according to the load speculative request to a load queue of the first processor core when the cacheline of the L1 memory cache is in the MSPEC state.
Dependencies are inferred from the claim text.