Data processing device
AssigneeRenesas Electronics Corporation
InventorsSugako Ohtani, Hiroyuki Kondo
Life of this patent
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Abstract
A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit.
Claims10
A data processing device executing a division instruction, the data processing device comprising:
- a plurality of registers;
- and
- a decoder that decodes instructions, including the division instruction, the division instruction including register information specifying one of the registers for dividend data and sign information for the dividend data,
- wherein the data processing device is configured to:
- determine whether the dividend data stored in the specified register is signed data or unsigned data based on the sign information,
- determine a position of a first effective bit of the dividend data, and
- perform the division instruction for a number of cycles,
- wherein the number of cycles is based on the position of the first effective bit.
A data processing device executing a division instruction, the data processing device comprising:
- a plurality of registers;
- and
- a decoder that decodes instructions, including the division instruction, the division instruction including register information specifying one of the registers for operation data and sign information for the operation data,
- wherein the data processing device is configured to:
- determine whether the operation data stored in the specified register is signed data or unsigned data based on the sign information,
- determine a position of a first effective bit of the operation data, and
- perform the division instruction for a number of cycles,
- wherein the number of cycles is based on the position of the first effective bit.
Dependencies are inferred from the claim text.