System and method for performing computational storage utilizing a hardware accelerator

A hardware accelerator device for performing computational storage and connectable to a central processing unit (CPU) and a solid state memory via a bus, the hardware accelerator device comprising:

• a dedicated buffer memory residing on the hardware accelerator device;
• a hardware accelerator in communication with the dedicated buffer memory and configured to:
• receive computation data from the CPU computing device via the bus;
• perform a check pointing operation on the received computation data to generate check point data;
• store the generated check point data on the dedicated buffer memory residing on the hardware accelerator device;
• and
• transmit the check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU;
• wherein:
• the hardware accelerator being configured to receive the computation data comprises the hardware accelerator being configured to receive a plurality of packets of computation data, each packet comprising W bytes;
• and
• the hardware accelerator being configured to perform the check pointing operation on the computation data comprising the hardware accelerator being configured to generate a packet of check point data based on each packet of computation data received and to perform compression of the computation data.

A system for performing computational storage comprising:

• a central processing unit (CPU);
• a solid state memory;
• a hardware accelerator device connected to the CPU and the solid state memory via a bus, the hardware accelerator device comprising:
• a dedicated buffer memory residing on the hardware accelerator device;
• a hardware accelerator in communication with the dedicated buffer memory and configured to:
• receive computation data from the CPU computing device via the bus, the computation data comprising a plurality of packets of computation data, each packet comprising W bytes;
• perform a check pointing operation on the received computation data to generate, for each packet of computation data, a packet of check point data, wherein the packet of check point data is compressed;
• store the generated packets of check point data on the dedicated buffer memory residing on the hardware accelerator device;
• and
• transmit the packets of check point data directly from the dedicated buffer memory to a solid state memory connected to the hardware accelerator device via the bus for storage, wherein transmitting the check point data bypasses the CPU;
• and
• the CPU configured to:
• determine a size of each packet of check point data;
• store metadata that includes the size of the packet of check point data and a storage location on the solid state memory at which the packet of check point data is stored.