Timer, electronic apparatus, and vehicle
AssigneeSeiko Epson Corporation
InventorMasayuki Kamiyama
Life of this patent
Estimating the term…
Abstract
A timer includes a timing counter configured to generate a timing datum, a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter, and an interface circuit configured to receive an access signal, wherein the timing counter is an asynchronous counter, and the clock pulse signal generation circuit generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal.
Claims10
A timer comprising:
- a timing counter configured to generate a timing datum;
- a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter;
- and
- an interface circuit configured to receive an access signal, wherein
- the timing counter is an asynchronous counter,
- the clock pulse signal generation circuit
- generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and
- generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal, and
- the second pulse width is a length obtained by multiplying a period of a source clock signal by 2 to N-th power, N representing a natural number.
A timer comprising:
- a timing counter configured to generate a liming datum:
- a clock pulse signal generation circuit configured to generate a clock pulse signal used to operate the timing counter:
- an interface circuit configured to receive an access signal, and
- a read buffer configured to obtain and hold, at predetermined timing, the timing datum generated by the timing counter, wherein
- the timing counter is an asynchronous counter, and
- the clock pulse signal generation circuit
- generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and
- generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal,
- the interface circuit outputs the timing datum held by the read buffer when receiving the access signal requesting reading of the timing datum, and
- the timing counter generates the timing datum with a predetermined period irrespective of whether or not the interface circuit received the access signal.
A timer comprising:
- a timing counter configured to generate a timing datum;
- signal used to operate the timing counter, and
- an interface circuit configured to receive an access signal wherein
- the timing counter is an asynchronous counter,
- the clock pulse signal generation circuit
- generates the clock pulse signal having a first pulse width when there is a possibility that the interface circuit receives the access signal, and
- generates the clock pulse signal having a second pulse width longer than the first pulse width when there is no possibility that the interface circuit receives the access signal, and
- the timing datum includes time information of a year, a month, a day, an hour, a minute, and a second.
Dependencies are inferred from the claim text.