Semiconductor device test socket

A test socket for electrical connection between a semiconductor device and a test board, the test socket comprising:

• a base layer having a first surface and a second surface opposing the first surface, and including external connection pads formed at a pitch corresponding to electrode terminals of the test board on the second surface;
• a plurality of circuit patterns formed to be partially exposed onto a surface of the base layer and rearranged at a pitch corresponding to the external connection pads;
• a plurality of electrode patterns formed on the first surface to be electrically connected to the circuit patterns and external connection terminals of the semiconductor device, and disposed at a pitch corresponding to the external connection terminals;
• an elastic layer surrounding the electrode patterns so that portions of the electrode patterns are exposed;
• and
• an inner side dam and an outer side dam disposed inside and outside the elastic layer, respectively, to support the elastic layer, the inner side dam comprising a first inner side dam and a second inner side dam, wherein the first inner side dam is adjacent to the elastic layer and the second inner side dam is disposed to be inwardly spaced apart from the first inner side dam.

A manufacturing method of a test socket for electrical connection between a semiconductor device and a test board, the manufacturing method comprising:

• a substrate preparation operation of preparing a substrate;
• an external connection pad formation operation of forming a plurality of external connection pads on a bottom surface of the substrate;
• a circuit pattern formation operation of forming a base layer on the substrate and rearranging circuit patterns for electrical connection with the external connection pads on the base layer;
• an electrode pattern formation operation of forming electrode patterns on the base layer so as to be electrically connected to the circuit patterns and external connection terminals of the semiconductor device, wherein the electrode pattern formation operation comprises:
• a first electrode pattern formation operation of forming first electrode patterns electrically connected to the circuit patterns;
• a second electrode pattern formation operation of forming second electrode patterns electrically connected to the first electrode patterns;
• a third electrode pattern formation operation of forming third electrode patterns electrically connected to the second electrode patterns;
• and
• a fourth electrode pattern formation operation of forming fourth electrode patterns electrically connected to the third electrode patterns and exposed onto an upper surface of an elastic layer;
• and
• an elastic layer formation operation of forming the elastic layer surrounding the electrode patterns on the base layer so that portions of the electrode patterns are exposed.