Method for semiconductor wafer inspection and system thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien-Huei Chen, Hung-Yi Chung, Xiaomeng Chen
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Abstract
A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.
Claims20
A method for semiconductor wafer inspection, comprising:
- scanning the semiconductor wafer to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect;
- transforming the design map and the scanned map to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map;
- and
- self-monitoring the transforming accuracy by comparing a location of the programmed defect on the transformed inspection map and locations of a pair of care area markers on the transformed inspection map.
A method for semiconductor wafer inspection, comprising:
- forming a plurality of programmed defects on a semiconductor wafer according to a plurality of expected locations on a design map;
- scanning the semiconductor wafer along a first swath to acquire a scanned map;
- detecting at least an actual location of at least one of the programmed defect in the scanned map;
- obtaining a transformed inspection map based on the design map and the scanned map to ascertain a first offset between the expected location and the actual location;
- and
- applying an adjusted mapping calculation in scanning the semiconductor wafer along a second swath to acquire another scanned map having a second offset less than the first offset.
A system for semiconductor wafer inspection, comprising:
- a computing apparatus configured to provide a design map having a first programmed defect on an expected location;
- a patterning apparatus coupled to the computing apparatus and configured to form the first programmed defect on an actual location of the semiconductor wafer according to the design map;
- and
- an inspecting apparatus coupled to the computing apparatus and configured to scan the semiconductor wafer to acquire a scanned map;
- wherein the computing apparatus is further configured to generate a transformed inspection map to ascertain an offset between the expected location and the actual location, and the transforming accuracy of the transformed inspection map is self-monitored by comparing a location of the programmed defect on the transformed inspection map and locations of a pair of care area markers on the transformed inspection map.
Dependencies are inferred from the claim text.