Electrochemical plating system and method of using

A method of forming a semiconductor structure, comprising:

• forming a plurality of contact openings in a dielectric layer over a substrate, the plurality of contact openings comprising a plurality of first contact openings in a first region of the substrate and a plurality of second contact openings in a second region of the substrate, the plurality of first contact openings having a highest line-end density in the plurality of contact openings;
• forming a barrier layer along sidewalls and bottoms of the plurality of contact openings and over the dielectric layer;
• forming a seed layer over the barrier layer;
• and
• performing an electrochemical plating (ECP) process to fill the plurality of contact openings with a conductive layer, wherein performing the ECP process comprises:
• in situ monitoring an interface resistance between an electroplated metal and an electrolyte in a plating solution as the ECP process continues;
• and
• adjusting a composition of the plating solution in response to the interface resistance being below a threshold resistance that is associated with the highest line-end density.

A method of forming a semiconductor structure, comprising:

• depositing a dielectric layer on a substrate;
• etching the dielectric layer to form a plurality of contact openings having different line-end densities in the dielectric layer, a plurality of first contact openings in the plurality of contact openings having the highest line-end density;
• forming a seed layer along surfaces of the plurality of contact openings;
• contacting the seed layer with a plating solution comprising a salt of a metal, an organic additive and an electrolyte;
• depositing the metal onto the seed layer by electroplating;
• in situ measuring an interface resistance between the electroplated metal and the electrolyte as the metal being deposited;
• and
• increasing a concentration of the organic additive in response to the interface resistance being below a threshold resistance below which voids are formed in the plurality of first contact openings, wherein the threshold resistance is determined using a layout data of an integrated circuit.