Continuous time linear equalization circuit
AssigneeNXP B.V.
InventorsSiamak Delshadpour, Xu Zhang, Tong Liu, Samuel Michael Palermo
Life of this patent
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Abstract
A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes a passive CTLE circuit and an active CTLE circuit. The active CTLE circuit includes a differential transistor pair and the output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.
Claims20
A continuous time linear equalization (CTLE) circuit, comprising a passive CTLE and an active CTLE circuit including a differential transistor pair coupled with each other via a degeneration impedance circuit of an order equal to or higher than two, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair, wherein the degeneration impedance circuit includes a resistive component, and wherein the active CTLE circuit is configured to adjust a DC gain by adjusting the resistive component.
A continuous time linear equalization (CTLE) circuit, comprising:
- a passive CTLE circuit;
- and
- an active CTLE circuit including a differential transistor pair, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair;
- and
- wherein the passive CTLE circuit includes a second order impedance circuit.
A continuous time linear equalization (CTLE) circuit, comprising:
- a passive CTLE circuit including a second order impedance circuit;
- and
- an active CTLE circuit including a differential transistor pair, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair, wherein the active CTLE circuit includes a second or higher order degeneration impedance circuit coupled between sources or emitters of the differential transistor pair;
- and
- a DC gain stage coupled with the active CTLE circuit to compensate for a DC loss due to the passive CTLE circuit.
A continuous time linear equalization (CTLE) circuit, comprising a passive CTLE and an active CTLE circuit including a differential transistor pair coupled with each other via a degeneration impedance circuit of an order equal to or higher than two, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair, wherein the degeneration impedance circuit is a second order degeneration impedance circuit including a capacitor, a resistor and an inductor coupled in a series and a resistor coupled in parallel with the series.
A continuous time linear equalization (CTLE) circuit, comprising a passive CTLE and an active CTLE circuit including a differential transistor pair coupled with each other via a degeneration impedance circuit of an order equal to or higher than two, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair, wherein the degeneration impedance circuit is a third order degeneration impedance circuit including a capacitor, a resistor and an inductor coupled in a series and a resistor coupled in parallel with the series, wherein a capacitor and a resistor is coupled to the inductor in parallel.
A continuous time linear equalization (CTLE) circuit, comprising:
- a passive CTLE circuit including a first order impedance circuit;
- a gain stage to compensate for a DC loss;
- and
- an active CTLE circuit including a differential transistor pair, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.
A continuous time linear equalization (CTLE) circuit, comprising:
- a passive CTLE circuit including a first order impedance circuit, wherein the passive CTLE is configured to add poles and zeros to an AC response of the passive CTLE circuit which increases the peaking gain of the CTLE;
- and
- an active CTLE circuit including a differential transistor pair, wherein an output of the passive CTLE is configured to drive gates or bases of the differential transistor pair.
Dependencies are inferred from the claim text.