Phase locked loop with phase error signal used to control effective impedance

An integrated circuit comprising a die and a phase locked loop circuit on the die, the phase locked loop circuit to generate a timing signal, the phase locked loop circuit having

• a phase detector to receive a reference signal and a generated signal and to generate an output representing a phase difference between the reference signal and the generated signal;
• an impedance network to generate a control signal from an input stimulus, wherein the impedance network has at least one of an effective resistance and an effective capacitance that is varied as a function of the output, and wherein the control signal is correspondingly varied;
• and
• an oscillator to generate the timing signal as a function of the control signal, the generated signal being dependent on the timing signal.

A method of operation of a phase locked loop circuit, the method comprising:

• with a phase detector, receiving a reference signal and a generated signal and generating an output representing a phase difference between the reference signal and the generated signal;
• generating a control signal from an input stimulus using an impedance network, wherein the impedance network has at least one of a variable effective resistance and a variable effective capacitance, and wherein generating the control signal comprises controlling the at least one of the variable effective resistance or the variable effective capacitance in accordance with the output, so as to correspondingly vary the control signal;
• and
• using an oscillator to controllably generate the generated signal as a function of the control signal.