Phase-locked loop circuitry and method to prevent fractional N spurious outputs in radar phase-locked loop

A method of preventing fractional spurs inside a radar frequency band having a frequency range including a minimum frequency and a maximum frequency, the method comprising:

• generating, by a first phase-locked loop (PLL), a ramping signal within the radar frequency band based on a first reference signal;
• generating, by a system clock, a second reference signal having a common system reference frequency;
• generating, by a second PLL, the first reference signal based on the second reference signal;
• and
• transmitting, by the second PLL, the first reference signal to the first PLL.

A radar signal generator, comprising:

• a first phase-locked loop (PLL) configured to receive a first reference signal having a first reference frequency and generate a radar ramping signal based on the first reference signal, wherein the radar ramping signal varies between two radar frequencies that are in a radar frequency band defined by a minimum radar frequency and a maximum radar frequency;
• a system clock configured to generate a second reference signal having a common system reference frequency;
• and
• a second PLL configured to receive the second reference signal from the system clock, generate the first reference signal based on the second reference signal, and provide the first reference signal to the first PLL.