Parallel rounding for conversion from binary floating point to binary coded decimal
AssigneeInternational Business Machines Corporation
InventorsStefan Payer, Silvia Melitta Mueller, Razvan Peter Figuli, Revital Arieli
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Abstract
Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.
Claims20
A computer-implemented method comprising:
- receiving, by a floating point unit (FPU), a binary floating point (BFP) value, wherein the BFP value comprises a significand, and wherein the significand comprises an integer part and a fractional part;
- transmitting, by the FPU, the integer part of the BFP to a conversion register and a duplicate BFP value to an adder;
- converting, by the conversion register, the integer part of the BFP value to a binary coded decimal (BCD) value and transmitting the BCD value to the adder;
- determining, in parallel to the converting, whether to round the BCD value received from the conversion register, based on a fractional part of the duplicate BFP value;
- and
- performing, in parallel to the converting and by the adder, a rounding operation on the BCD value based on the rounding determination.
A system comprising:
- a memory having computer readable instructions;
- and
- one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
- receiving, by a floating point unit (FPU), a binary floating point (BFP) value, wherein the BFP value comprises a significand, and wherein the significand comprises an integer part and a fractional part;
- transmitting, by the FPU, the integer part of the BFP to a conversion register and a duplicate BFP value to an adder;
- converting, by the conversion register, the integer part of the BFP value to a binary coded decimal (BCD) value and transmitting the BCD value to the adder;
- determining, in parallel to the converting, whether to round the BCD value received from the conversion register, based on a fractional part of the duplicate BFP value;
- and
- performing, in parallel to the converting and by the adder, a rounding operation on the BCD value based on the rounding determination.
A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
- receiving, by a floating point unit (FPU), a binary floating point (BFP) value, wherein the BFP value comprises a significand, and wherein the significand comprises an integer part and a fractional part;
- transmitting, by the FPU, the integer part of the BFP to a conversion register and a duplicate BFP value to an adder;
- converting, by the conversion register, the integer part of the BFP value to a binary coded decimal (BCD) value and transmitting the BCD value to the adder;
- determining, in parallel to the converting, whether to round the BCD value received from the conversion register, based on a fractional part of the duplicate BFP value;
- and
- performing, in parallel to the converting and by the adder, a rounding operation on the BCD value based on the rounding determination.
Dependencies are inferred from the claim text.