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US 11,218,225 B1Granted
Analog receiver equalizer architectures for high-speed wireline and optical applications
AssigneeMarvell Asia Pte Ltd
InventorBasel Alnabulsi
Life of this patent
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Abstract
The present invention is directed to communication method and techniques. In a specific embodiment, the present invention provides a receiver that interleaves data signal n-ways for n slices. Each of the n slices includes feedforward equalizer and decision feedback equalizers that are coupled to other slices. Each of the n slices also includes an analog-to-digital converter section that includes data and error slicers. There are other embodiments as well.
Claims18
A receiver comprising:
- an analog front end (AFE) circuit configured to process data signals received from a communication channel;
- a time-interleave (TI) block configured to interleave processed data signals from the AFE circuit n-ways;
- an array of n slices comprising a first slice and a second slice, the array of n slices being configured to perform analog-to-digital conversion (ADC) processes and output a digital data stream;
- and
- a digital signal processor (DSP) coupled to the array of n slices and configured to process the digital data stream;
- wherein the first slice comprises:
- a first feedforward equalizer (FFE) configured to equalize a first interleaved signal from the TI block using one or more precursor values from at least the second slice;
- a first decision device coupled to the first FFE and configured to provide a first equalized data stream using one or more postcursor values from at least a third slice;
- and
- a first converter coupled to the first decision device and configured to perform a first ADC process on the first equalized data stream.
7 more elements
A signal processing circuit comprising:
- a time-interleave (TI) block configured to interleave processed incoming data signals n-ways;
- and
- an array of n slices comprising a first slice and a second slice, the array of n slices being configured to perform analog-to-digital conversion (ADC) processes and output a digital data stream, the first slice comprising:
- a first feedforward equalizer (FFE) comprising a first summer and configured to equalize a first interleaved signal from the TI block using one or more precursor values from at least the second slice;
- a first decision device comprising a first variable gain amplifier (VGA) coupled to the first FFE and configured to provide a first equalized data stream using one or more postcursor values from at least a third slice;
- and
- a first converter comprising a first plurality of slicers and configured to perform a first ADC process on the first equalized data stream.
4 more elements
Dependencies are inferred from the claim text.