Tracking analog-to-digital converter with adaptive slew rate boosting
AssigneeAllegro MicroSystems, LLC
InventorsLeandro Fuentes, Manuel Rivas, Patricio Hernan Perez Preiti, Bruno Luis Uberti, Alejandro Gabriel Milesi
Life of this patent
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Abstract
A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.
Claims17
A tracking analog-to-digital converter (ADC) comprising:
- a comparator having a first input to receive an analog input signal, a second input to receive an analog feedback signal, and an output to provide a digital error signal responsive to a comparison between the analog input signal and the analog feedback signal;
- a slew rate detection circuit to generate a slew rate detection signal responsive to a slew rate of the analog input signal;
- an error adjustment circuit having a first input to receive the digital error signal, a second input to receive the slew rate detection signal, and an output to provide an adjusted error signal responsive to the digital error signal and the slew rate detection signal;
- an integrator having an input to receive the adjusted error signal and an output to provide a digital output signal having a value that increases or decreases at each period of a clock according to the adjusted error signal;
- and
- a digital-to-analog converter (DAC) having an input to receive the digital output signal and an output to provide the analog feedback signal responsive to the digital output signal.
A tracking analog-to-digital converter (ADC) comprising:
- a comparator having a first input to receive an analog input signal, a second input to receive an analog feedback signal, and an output to provide a digital error signal responsive to a comparison between the analog input signal and the analog feedback signal;
- a slew rate detection circuit to generate a slew rate detection signal responsive to a slew rate of the analog input signal;
- a clock adjustment circuit having an input to receive the slew rate detection signal, and an output to provide commands to adjust a frequency of a clock responsive to the slew rate detection signal;
- an integrator having an input to receive the digital error signal and an output to provide a digital output signal having a value that increases or decreases at each period of the clock according to the digital error signal;
- and
- a digital-to-analog converter (DAC) having an input to receive the digital output signal and an output to provide the analog feedback signal responsive to the digital output signal.
A tracking analog-to-digital converter (ADC) comprising:
- means for generating a digital error signal responsive to a comparison between an analog input signal and an analog feedback signal;
- means for integrating the digital error signal or an adjusted version of the digital error signal over multiple clock periods to generate a digital output signal;
- means for converting the digital output signal to the analog feedback signal;
- means for detecting a slew rate limit condition of the tracking ADC;
- and
- means for adjusting one or more operational parameters of the tracking ADC in response to detection of the slew rate limit condition.
Dependencies are inferred from the claim text.