US 11,216,365 B1Granted

Maintenance of non-volaitle memory on selective namespaces

AssigneeRadian Memory Systems, Inc.

InventorsAndrey V. Kuzmin, James G. Wayda

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Abstract

This disclosure provides for improvements in managing multi-drive, multi-die or multi-plane NAND flash memory. In one embodiment, the host directly assigns physical addresses and performs logical-to-physical address translation in a manner that reduces or eliminates the need for a memory controller to handle these functions, and initiates functions such as wear leveling in a manner that avoids competition with host data accesses. A memory controller optionally educates the host on array composition, capabilities and addressing restrictions. Host software can therefore interleave write and read requests across dies in a manner unencumbered by memory controller address translation. For multi-plane designs, the host writes related data in a manner consistent with multi-plane device addressing limitations. The host is therefore able to “plan ahead” in a manner supporting host issuance of true multi-plane read commands.

Claims20

Dependent claims

A method of configuring a memory controller for nonvolatile memory, the nonvolatile memory comprising memory dies, said method comprising, with at least one host processor:

classifying addressable memory space into a first set of addresses and a second set of addresses;
programing the memory controller for nonvolatile memory to organize the addressable memory space so as to direct a number of data accesses, when addressed to the first set of addresses, to the first number of the memory dies, and so as to direct the number of data accesses, when addressed to the second set of addresses, to the second number of the memory dies, wherein the second number of the memory dies is selectively different from the first number of the memory dies;
tracking maintenance needed for nonvolatile memory associated with the first set of addresses and issuing to the memory controller a first request to perform maintenance for nonvolatile memory associated with the first set of addresses, wherein the memory controller is to responsively direct one or more commands to the first number of the memory dies to perform the maintenance for the first set of addresses;
and
tracking maintenance needed for nonvolatile memory associated with the second set of addresses and issuing to the memory controller a second request to perform maintenance for nonvolatile memory associated with the second set of addresses, wherein the memory controller is to responsively direct one or more commands to the second number of the memory dies to perform the maintenance for the second set of addresses.

2 more elements

An apparatus to configure a memory controller for nonvolatile memory, the nonvolatile memory comprising memory dies, said apparatus comprising instructions stored on a nontransitory medium, the instructions when executed to cause at least one host processor to:

classify addressable memory space into a first set of addresses and a second set of addresses;
program the memory controller for nonvolatile memory to organize the addressable memory space so as to direct a number of data accesses, when addressed to the first set of addresses, to the first number of the memory dies, and so as to direct the number of data accesses, when addressed to the second set of addresses, to the second number of the memory dies, wherein the second number of the memory dies is selectively different from the first number of the memory dies;
track maintenance needed for nonvolatile memory associated with the first set of addresses and issue to the memory controller a first request to perform maintenance for nonvolatile memory associated with the first set of addresses, wherein the memory controller is to responsively direct one or more commands to the first number of the memory dies to perform the maintenance for the first set of addresses;
and
track maintenance needed for nonvolatile memory associated with the second set of addresses and issue to the memory controller a second request to perform maintenance for nonvolatile memory associated with the second set of addresses, wherein the memory controller is to responsively direct one or more commands to the second number of the memory dies to perform the maintenance for the second set of addresses.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/833,547Filed 28 Mar 2020 · continuation
Priority: 28 Jan 2013
Granted: 4 Jan 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0611
Improving I/O performance: in relation to response time
G06F 3/0638
Making use of a particular technique: organizing or formatting or addressing of data

Family

Application61/757,464Us provisional application · filed 28 Jan 2013
Application13/767,723Parent of this continuation-in-part · filed 14 Feb 2013
Application14/047,193Parent of this continuation · filed 7 Oct 2013
Application14/951,708Parent of this continuation · filed 25 Nov 2015
US 9,229,854 B1Parent of this continuation · filed 21 Jan 2016
Application15/346,641Parent of this continuation · filed 8 Nov 2016
US 9,519,578 B1Parent of this continuation · filed 13 Dec 2016
US 9,652,376 B2Parent of this continuation-in-part · filed 16 May 2017
Application15/621,888Parent of this continuation · filed 13 Jun 2017
US 9,710,377 B1Parent of this continuation · filed 18 Jul 2017
Application16/570,922Parent of this continuation · filed 13 Sep 2019
US 10,445,229 B1Parent of this continuation · filed 15 Oct 2019
Application14/047,193Parent of this continuation-in-part
US 11,188,457 B1Related patent
US 2014/0215129 A1Published application
US 11,216,365 B1This patent

From the US filing history. Foreign family members aren’t listed.