Method and apparatus for performing field programmable gate array packing with continuous carry chains
AssigneeIntel Corporation
InventorsMartin Langhammer, Gregg William Baeckler
Life of this patent
Estimating the term…
Abstract
A method for designing a system on a target device includes identifying a length for a carry chain that is supported by predefined quanta of a resource on the target device. A plurality of logical adders is mapped onto a single logical adder implemented on the carry chain subject to the identified length to increase logic utilization in a design for the system.
Claims25
A method for designing a system on a target device, comprising:
- identifying a length for a carry chain that is supported by predefined quanta of a resource on the target device;
- mapping a plurality of logical adders onto a single logical adder implemented on the carry chain subject to the identified length to increase logic utilization in a design for the system;
- and
- designating a first bit position on the carry chain where no overflow occurs when summing values from a first logical adder that values from a second logical adder are summed on the carry chain and placed at a second bit position next to the first bit position.
A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, the method comprising:
- mapping a plurality of logical adders onto a single logical adder implemented on a carry chain in a design for the system;
- and
- designating a first bit position on the carry chain where no overflow occurs when summing values from a first logical adder of the plurality of logical adders that values from a second logical adder of the plurality of logical adders are summed on the carry chain and placed at a second bit position next to the first bit position.
A system designer, comprising:
- a design generation unit that generates a hardware description language (HDL) of a system to be implemented on a target device;
- a synthesis unit that synthesizes the HDL of the system on the target device to generate a synthesized system;
- a placement unit that places the synthesized system on the target device;
- and
- a carry chain packing unit that maps a plurality of logical adders onto a single logical adder implemented on a carry chain to increase logic utilization in a design for the system, wherein the carry chain packing unit is implemented on one of the design generation unit, the synthesis unit, and the placement unit, and wherein the carry chain packing unit designates a first bit position on the carry chain where no overflow occurs when summing values from a first logical adder that values from a second logical adder are summed on the carry chain and placed at a second bit position next to the first bit position.
Dependencies are inferred from the claim text.