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US 11,211,934 B2Granted
Apparatus to improve lock time of a frequency locked loop
AssigneeIntel Corporation
InventorsPraveen Mosalikanti, Qi Wang, Mark L. Neidengard, Vaughn J. Grossnickle, Nasser A. Kurd
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Abstract
An apparatus is provided which comprises: a frequency locked loop (FLL) comprising an oscillator including a plurality of delay stages, wherein an output of each delay stage is counted to determine a frequency of the FLL; and one or more circuitries coupled to the FLL to adjust a power supply to the FLL according to the determined frequency of the FLL.
Claims16
An apparatus comprising:
- a low dropout regulator with adjustable reference, wherein the low dropout regulator is to receive a first power supply voltage, and is to generate a second power supply voltage according to the adjustable reference;
- an oscillator powered by the second power supply voltage;
- and
- a set of counters coupled to the oscillator, wherein the set of counters is to determine a frequency of the oscillator, wherein the set of counters includes:
- a first counter having a clock input coupled to an output of a first delay stage of the oscillator;
- and
- a second counter having an inverse clock input coupled to the output of the first delay stage.
4 more elements
An apparatus comprising:
- a frequency locked loop including an oscillator;
- a supply generator with an adjustable current source, wherein the supply generator is to receive a first power supply voltage, and is to generate a second power supply voltage for the oscillator according to the adjustable current source;
- and
- logic to adjust the adjustable current source according to a frequency of the oscillator, wherein the logic includes a set of counters coupled to multiple stages of the oscillator, wherein the set of counters is to generate multiple outputs indicative of frequency at each stage of the multiple stages.
1 more element
A system comprising:
- a memory;
- a processor coupled to the memory;
- and
- a antenna communicatively coupled to the processor, wherein the processor includes:
- a low dropout regulator with adjustable reference, wherein the low dropout regulator is to receive a first power supply voltage, and is to generate a second power supply voltage according to the adjustable reference;
- an oscillator powered by the second power supply voltage;
- and
- a set of counters coupled to the oscillator, wherein the set of counters is to determine a frequency of the oscillator, wherein the set of counters includes:
- a first counter having a clock input coupled to an output of a first delay stage of the oscillator;
- and
- a second counter having an inverse clock input coupled to the output of the first delay stage.
8 more elements
Dependencies are inferred from the claim text.