Analogue-to-digital conversion method of pipelined analogue-to-digital converter and pipelined analogue-to-digital converter

A pipelined analog-to-digital converter implementing a pipelined analog-to-digital conversion method employing T pipeline stages for analog-to-digital conversion, wherein T≥2, and performing the analog-to-digital conversion in an ith pipeline stage comprises three steps, wherein 1≤i≤T,

• step 1. sampling period of the pipeline stages:
• sampling the pipeline stages, wherein if i=1, the pipeline stage is a first pipeline stage and is executed according to step 1.1;
• and if 1<i≤T, the pipeline stage is executed according to step 1.2;
• step 1.1. inputting an analog signal to be converted into the first pipeline stage, wherein an input signal of a digital-to-analog converter of the first pipeline stage is zero and an output signal of the digital-to-analog converter of the first pipeline stage is also zero, a difference between the analog signal to be converted and the output signal of the digital-to-analog converter of the first pipeline stage which is namely the analog signal to be converted, is sent into an analogue-to-digital converter of the first pipeline stage for sampling, and step 2 is executed after the sampling is completed;
• and
• step 1.2:
• when step 1 is executed in the ith pipeline stage, executing step 3 in an (i−1)th pipeline stage, inputting an analog signal obtained by amplifying a quantization residual of the (i−1)th pipeline stage by an amplifier of the (i−1)th pipeline stage into the ith pipeline stage, and meanwhile, performing one more quantization on the quantization residual of the (i−1)th pipeline stage by an analogue-to-digital converter of the (i−1)th pipeline stage, sending an M-bit quantization result obtained by the one more quantization into a digital-to-analog converter of the ith pipeline stage to generate an analog output signal when the M-bit quantization result is inputted and record the analog output signal as a first analog output signal of an analogue-to-digital converter of the ith pipeline stage, and executing step 2 after the sampling is completed;
• step 2. quantization period of the pipeline stages:
• quantizing the pipeline stages, wherein if i=1, the pipeline stage is the first pipeline stage and is executed according to step 2.1;
• and if i<i≤T, the pipeline stage is executed according to step 2.2;
• step 2.1. quantizing the analog signal to be converted by the analogue-to-digital converter of the first pipeline stage to obtain an N-bit quantization result and send the N-bit quantization result into the digital-to-analog converter of the first pipeline stage, performing, by the digital-to-analog converter of the first pipeline stage, digital-to-analogue conversion on the N-bit quantization result inputted by the analogue-to-digital converter of the first pipeline stage, outputting an analog output signal during N-bit inputting, and executing step 3 after the quantizing is completed;
• and
• step 2.2. when step 2 is executed in the ith pipeline stage, executing step 1 in the (i−1)th pipeline stage, quantizing the inputted analog signal by the amplifying analogue-to-digital converter of the ith pipeline stage to obtain an N-bit quantization result and send the N-bit quantization result into the digital-to-analog converter of the ith pipeline stage, performing, by the digital-to-analog converter of the ith pipeline stage, digital-to-analogue conversion together on the N-bit quantization result inputted by the analogue-to-digital converter of the ith pipeline stage and the M-bit quantization result inputted by the (i−1)th pipeline stage, outputting an analog output signal during (N+M)-bit inputting and record the analog output signal as a second analog output signal of the digital-to-analog converter of the ith pipeline stage, and executing step 3 after the sampling is completed;
• and
• step 3. amplification and extra quantization period of the pipeline stages:
• amplifying and extra quantizing the pipeline stages, wherein if i=1, the pipeline stage is the first pipeline stage and is executed according to step 3.1, if 2<i<T, the pipeline stage is executed according to step 3.2, and if i=T, the pipeline stage is a last pipeline stage and is executed according to step 3.3;
• step 3.1. a difference between the analog signal to be converted and the analog output signal outputted by the digital-to-analog converter of the first pipeline stage during N-bit inputting being a quantization residual of the first pipeline stage, amplifying the quantization residual of the first pipeline stage by an amplifier of the first pipeline stage and then inputting the quantization residual of the first pipeline stage into a second pipeline stage, and meanwhile, performing one more quantization on the quantization residual of the first pipeline stage by the analogue-to-digital converter of the first pipeline stage, and sending an obtained M-bit quantization result into a digital-to-analog converter of the second pipeline stage, wherein an (N+M)-bit quantization result of the first pipeline stage is obtained by the two quantization in step 2.1 and step 3.1;
• step 3.2. a difference between the quantization residual of the (i−1)th pipeline stage and the second analog output signal outputted by the digital-to-analog converter of the ith pipeline stage being a quantization residual of the ith pipeline stage, amplifying the quantization residual of the ith pipeline stage by an amplifier of the ith pipeline stage and then inputting the quantization residual of the ith pipeline stage into an (i+1)th pipeline stage, and meanwhile, performing one more quantization on the quantization residual of the ith pipeline stage by the analogue-to-digital converter of the ith pipeline stage, and sending an obtained M-bit quantization result into a digital-to-analog converter of the (i+1)th pipeline stage, wherein an (N+M)-bit quantization result of the ith pipeline stage is obtained by the two quantization in step 2.2 and step 3.2;
• and
• step 3.3. a difference between a quantization residual of the (T−1)th pipeline stage and a second analog output signal outputted by a digital-to-analog converter of a Tth pipeline stage being a quantization residual of the Tth pipeline stage, performing one more quantization on the quantization residual of the Tth pipeline stage by an analogue-to-digital converter of the Tth pipeline stage to obtain an M-bit quantization result, wherein an (N+M)-bit quantization result of the Tth pipeline stage is obtained by the two quantization in step 2.2 and step 3.3;
• wherein 1≤N, 1≤M, and M≤N;
• the pipelined analog-to-digital converter comprises pipeline stages, wherein T≥2, the T pipeline stages are coupled in a cascade manner, and an ith pipeline stage comprises an analogue-to-digital converter, a digital-to-analog converter and a subtractor, and 1≤i≤T, wherein:
• when i=1, namely in a first pipeline stage, an analog signal to be converted is inputted from an input terminal of the first pipeline stage, the input terminal of the first pipeline stage is connected with a positive input terminal of a subtractor of the first pipeline stage, an output terminal of the subtractor of the first pipeline stage is respectively connected with an input terminal of an amplifier of the first pipeline stage and an input terminal of an analogue-to-digital converter of the first pipeline stage, a first output terminal of the analogue-to-digital converter of the first pipeline stage is connected with a first input terminal of a digital-to-analog converter of the first pipeline stage, a second output terminal of the analogue-to-digital converter of the first pipeline stage is connected with a second input terminal of a digital-to-analog converter of a second pipeline stage, and an output terminal of the digital-to-analog converter of the first pipeline stage is connected with a negative input terminal of the subtractor of the first pipeline stage;
• an output terminal of an amplifier of the first pipeline stage is connected with an input terminal of the second pipeline stage;
• and the first output terminal of the analogue-to-digital converter of the first pipeline stage outputs an N-bit quantization result of a quantization period, the second output terminal of the analogue-to-digital converter of the first pipeline stage outputs an M-bit quantization result of an amplification and extra quantization period, and an (N+M)-bit quantization result of the first pipeline stage is obtained by two quantization;
• when 1<i<T, in the ith pipeline stage, an output terminal of an amplifier of an (i−1)th pipeline stage is connected with an input terminal of the ith pipeline stage, the input terminal of the ith pipeline stage is connected with a positive input terminal of the subtractor of the ith pipeline stage, an output terminal of the subtractor of the ith pipeline stage is respectively connected with an input terminal of the amplifier of the ith pipeline stage and an input terminal of the analogue-to-digital converter of the ith pipeline stage, a first output terminal of the analogue-to-digital converter of the ith pipeline stage is connected with a first input terminal of the digital-to-analog converter of the ith pipeline stage, a second output terminal of the analogue-to-digital converter of the ith pipeline stage is connected with a second input terminal of a digital-to-analog converter of an (i+1)th pipeline stage, and an output terminal of the digital-to-analog converter of the ith pipeline stage is connected with a negative input terminal of the subtractor of the ith pipeline stage;
• an output terminal of the amplifier of the ith pipeline stage is connected with an input terminal of the (i+1)th pipeline stage;
• and the first output terminal of the analogue-to-digital converter of the ith pipeline stage outputs the N-bit quantization result of the quantization period, the second output terminal of the analogue-to-digital converter of the ith pipeline stage the M-bit quantization result of the amplification and extra quantization period, and an (N+M)-bit quantization result of the ith pipeline stage is obtained by two quantization;
• and
• when i=T, in a Tth pipeline stage, an output terminal of an amplifier of a (T−1)th pipeline stage is connected with an input terminal of the Tth pipeline stage, the input terminal of the Tth pipeline stage is connected with a positive input terminal of a subtractor of the Tth pipeline stage, an output terminal of the subtractor of the Tth pipeline stage is connected with an input terminal of an analogue-to-digital converter of the Tth pipeline stage, a first output terminal of the analogue-to-digital converter of the Tth pipeline stage is connected with a first input terminal of a digital-to-analog converter of the Tth pipeline stage, the analogue-to-digital converter of the Tth pipeline stage further comprises a second output terminal, and an output terminal of the digital-to-analog converter of the Tth pipeline stage is connected with a negative input terminal of the subtractor of the Tth pipeline stage;
• and the first output terminal of the analogue-to-digital converter of the Tth pipeline stage outputs the N-bit quantization result of the quantization period, the second output terminal of the analogue-to-digital converter of the Tth pipeline stage outputs the M-bit quantization result of the amplification and extra quantization period, and an (N+M)-bit quantization result of the Tth pipeline stage is obtained by two quantization;
• wherein 1≤N, 1≤M, and M≤N.