High performance super-beta NPN (SBNPN)

An integrated circuit, comprising:

• a first dielectric layer located over a semiconductor layer having a first conductivity type, the first dielectric layer including an opening;
• a second dielectric layer between the first dielectric layer and the semiconductor layer, the second dielectric layer defining a first recess between the first dielectric layer and the semiconductor substrate at a first side of the opening, and a second recess between the first dielectric layer and the semiconductor substrate at a second opposite side of the opening;
• a first doped region of the semiconductor layer under the opening, the first doped region having a different second conductivity type and a first width;
• a second doped region of the semiconductor layer under the opening, the second doped region having the second conductivity type and underlying the first recess and the second recess.

An integrated circuit having an NPN bipolar transistor, the transistor comprising:

• an N-type collector region over a semiconductor substrate;
• a P-type base region over the collector region;
• an N-type emitter region within the base region;
• a silicon nitride layer located over the base region and including an opening;
• a silicon dioxide layer between the silicon nitride layer and the base region, the silicon dioxide layer defining a first recess between the silicon nitride layer and the base region at a first side of the opening, and a second recess between the silicon nitride layer and the semiconductor substrate at a second opposite side of the opening;
• and
• an N-type halo region under the opening that intersects a surface of the substrate and extends laterally with respect to the surface past the first and second recesses.