Bump connection placement in quantum devices in a flip chip configuration
AssigneeInternational Business Machines Corporation
InventorsDongbing Shao, Markus Brink
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Abstract
Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
Claims20
A computer-implemented method comprising:
- mapping, within a layout of a first surface in a flip chip configuration, a bump restriction area according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump positioned in the layout of the first surface in the flip chip configuration and a qubit chip element positioned in the layout of the first surface in the flip chip configuration;
- and
- depositing an electrically conductive material, outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:
- program instructions to map, within a layout of a first surface in a flip chip configuration, a bump restriction area according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump positioned in the layout of the first surface in the flip chip configuration and a qubit chip element positioned in the layout of the first surface in the flip chip configuration;
- and
- program instructions to deposit an electrically conductive material, outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
A computer system comprising one or more processors, one or more computer-readable memories, and one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices for execution by at least one of the one or more processors via at least one of the one or more memories, the stored program instructions comprising:
- program instructions to map, within a layout of a first surface in a flip chip configuration, a bump restriction area according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump positioned in the layout of the first surface in the flip chip configuration and a qubit chip element positioned in the layout of the first surface in the flip chip configuration;
- and
- program instructions to deposit an electrically conductive material, outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.
Dependencies are inferred from the claim text.