System and method for controlling CDR and CTLE parameters

A circuit for receiving serial data, the circuit having an input for receiving an analog input signal and comprising:

• a baud-rate clock and data recovery circuit;
• and
• a reference voltage control circuit for controlling a first reference voltage or a second reference voltage of the baud-rate clock and data recovery circuit,
• wherein the reference voltage control circuit comprises:
• a first sampler for sampling the analog input signal relative to a third reference voltage;
• a first pattern filter to select a bit pattern comprising three consecutive one bits;
• and
• a first accumulator for accumulating, in a register of the first accumulator, output values of the first sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter.

A circuit for receiving serial data, the circuit having an input for receiving an analog input signal and comprising:

• means for baud-rate clock and data recovery;
• and
• a reference voltage control circuit for controlling a first reference voltage or a second reference voltage of the means for baud-rate clock and data recovery,
• wherein the reference voltage control circuit comprises:
• a first sampler for sampling the analog input signal relative to a third reference voltage;
• a first pattern filter to select a bit pattern comprising three consecutive one bits;
• and
• a first accumulator for accumulating, in a register of the first accumulator, output values of the first sampler for samples corresponding to the second bit of each pattern matched by the first pattern filter.