Reduced flyback ESD surge protection

A method for protecting an integrated circuit (IC) from an electrostatic discharge (ESD) event, comprising:

• detecting the ESD event;
• causing an ESD protection circuit to enter an enable state by using a NAND-based latch to activate an ESD clamp to clamp a supply voltage in response to detecting the ESD event;
• after a predetermined protection period, causing the ESD protection circuit to enter a controlled disable state by gradually releasing the ESD clamp to reduce a flyback in the supply voltage;
• and
• after a predetermined ramp-down period, causing the ESD protection circuit to enter a disable state by opening the ESD clamp.

An electronic device, comprising:

• a supply node;
• a ground node;
• and
• a first electrostatic discharge (ESD) protection circuit coupled between the supply node and the ground node and comprising:
• a first ESD clamp configured to clamp the supply node when an ESD event is detected;
• a first driver coupled to the first ESD clamp and configured to activate the first ESD clamp for a predetermined protection period when the ESD event is detected;
• a first NAND-based latch configured to provide a first activation signal to cause the first driver to activate the first ESD clamp;
• and
• a first ramp-down driver coupled to the first ESD clamp and configured to gradually disable the first ESD clamp after a predetermined protection period.