Counter readout circuit
AssigneeMurata Manufacturing Co., Ltd.
InventorsSatoru Matsuyama, Satoshi Matsumura, Kazuhiro Nakamuta
Life of this patent
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Abstract
A counter readout circuit includes a plurality of counter registers and an output data computing unit. The plurality of counter registers, each includes a counter which counts per clock signal cycle. The output data computing unit includes a computing unit which adds, for output, the counter value of a counter register to the total clock count from a first timing to a second timing. The counter register is selected from the plurality of counter registers. The first timing is common to all of the plurality of counter registers. The second timing is a timing of selection of the selected counter register.
Claims5
A counter readout circuit comprising:
- a plurality of counter registers that each comprise a counter configured to count cycles of a clock signal;
- and
- an output data computing circuit configured to calculate a calculated data value by adding a counter value of a selected one of the plurality of counter registers to a total clock count, and configured to output the calculated data, wherein:
- the total clock count is a number of clock cycles between a first timing and a second timing,
- the first timing is a time at which the counter readout circuit receives a first data readout request common to all of the counter registers, and
- the second timing is a time at which the counter readout circuit receives a second data readout request specific to the selected one of the counter registers.
Dependencies are inferred from the claim text.