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US 11,200,363 B1Granted
Optimizing place-and-routing using a random normalized polish expression
AssigneePulsic Limited
InventorsMark Waller, Paul Clewes, Liang Gao, Jonathan Longrigg
Life of this patent
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Abstract
Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.
Claims19
A method comprising:
- generating a first expression;
- using a computer processor, using the first expression, generating a first place-and-route solution for an integrated circuit design, wherein the integrated circuit design comprises a plurality of cells, and the first place-and-route solution can comprise an interconnect routing path formed on different interconnect layers;
- generating a second expression;
- using the second expression, generating a second place-and-route solution for the integrated circuit design;
- generating a third expression;
- using the third expression, generating a third place-and-route solution for the integrated circuit design, wherein each of the first, second, and third place-and-route solutions are different from each other;
- calculating a first cost function for the first place-and-route solution;
- calculating a second cost function for the second place-and-route solution;
- calculating a third cost function for the third place-and-route solution;
- comparing the first, second, and third cost functions based on at least one of wire length or whitespace parameters;
- and
- based on the comparison of the first, second, and third cost functions, selecting one of the first, second, and third place-and-route solutions to obtain a selected place-and-route solution, and discarding the place-and-route solutions not selected.
9 more elements
A method comprising:
- generating a first expression;
- using a computer processor, using the first expression, generating a first place-and-route solution for an integrated circuit design, wherein the integrated circuit design comprises a plurality of cells, and the first place-and-route solution can comprise an interconnect routing path formed on different interconnect layers;
- generating a second expression;
- using the second expression, generating a second place-and-route solution for the integrated circuit design;
- generating a third expression;
- using the third expression, generating a third place-and-route solution for the integrated circuit design, wherein each of the first, second, and third expressions comprises a random normalized polish expression, and each of the first, second and third place-and-route solutions are different from each other;
- calculating a first cost function for the first place-and-route solution;
- calculating a second cost function for the second place-and-route solution;
- calculating a third cost function for the third place-and-route solution;
- comparing the first, second, and third cost functions based on at least one of wire length or whitespace parameters;
- and
- based on the comparison of the first, second, and third cost functions, selecting one of the first, second, and third place-and-route solutions to obtain a selected place-and-route solution.
9 more elements
Dependencies are inferred from the claim text.