Interrupt control device and interrupt control method between clock domains

An interrupt control device between clock domains, comprising:

• an interrupt sharing logic, configured to receive one or more original interrupt signals and generate a combined interrupt signal;
• and
• an interrupt processing logic, configured to output a processed interrupt signal to a processor according to the combined interrupt signal, so that the processor correspondingly executes an interrupt service routine;
• wherein when the interrupt service routine is executed, the processor sends a control signal to block further interrupt(s) and then the processor outputs an interrupt clear signal to change a respective interrupt signal to be negated among the one or more original interrupt signals, and after the interrupt processing logic detects the clearance of the respective interrupt signal, the interrupt processing logic generates the processed interrupt signal according to the combined interrupt signal again;
• wherein the original interrupt signals are generated by peripheral devices in a first clock domain, the processor is located in a second clock domain, the interrupt sharing logic is located in the first clock domain, and the interrupt processing logic is located in both of the first and second clock domains.