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US 11,199,869 B2Granted
Method and apparatus for outputting signals
AssigneeAgency for Defense Development
InventorsJong Pyo Han, Seo Hee Yang, Jae Ho Park
Life of this patent
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Abstract
This application relates to a method and apparatus for outputting signals. In one aspect, the apparatus includes a signal control unit configured to generate two or more control signals upon two or more conditions, which respectively correspond to the two or more control signals being satisfied. The apparatus also includes a signal output unit configured to output a final output signal depending on the two or more control signals upon an input signal being inputted into the signal output unit.
Claims9
A signal output apparatus comprising:
- a signal control unit configured to generate two or more control signals based on two or more conditions, which respectively correspond to the two or more control signals;
- and
- a signal output unit configured to output a final output signal depending on the two or more control signals and based on an input signal being inputted into the signal output unit;
- wherein the two or more conditions include a first condition and a second condition, and the two or more control signals include a first control signal and a second control signal, and
- wherein the signal control unit includes:
- a first control signal generating unit configured to generate the first control signal in response to the first condition being satisfied among a plurality of conditions;
- a second control signal generating unit configured to generate the second control signal in response to the second condition being satisfied among the plurality of conditions;
- a first control signal dividing unit including:
- a first dividing circuit configured to divide the first control signal into a first divided signal and a second divided signal;
- a first inverter connected to the first dividing circuit;
- and
- a first buffer connected to the first dividing circuit,
- wherein the first divided signal is configured to pass through the first inverter and the second divided signal is configured to pass through the first buffer;
- a second control signal dividing unit including:
- a second dividing circuit configured to divide the second control signal into a third divided signal and a fourth divided signal;
- a second inverter connected to the second dividing circuit;
- and
- a second buffer connected to the second dividing circuit,
- wherein, the third divided signal is configured to pass through the second inverter and the fourth divided signal is configured to pass through the second buffer;
- a first safety signal output unit configured to:
- compare the first divided signal which is an output of the first inverter and the second divided signal which is an output of the first buffer, the first divided signal and the second divided signal further configured to respectively pass through a first open-collector type inverter component and a second open-collector type inverter component, the first and the second open-collector type inverter components each including at least one inverter;
- determine that the first divided signal and the second divided signal are different after the first divided signal and the second divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a first discrete output unit of the first safety signal output unit, a first safety signal as one of a plurality of the control signals only when it is determined that the first divided signal and the second divided signal are different;
- and
- a second safety signal output unit configured to:
- compare the third divided signal which is an output of the second inverter and the fourth divided signal which is an output of the second buffer, the third divided signal and the fourth divided signal further configured to respectively pass through the first and the second open-collector type inverter components;
- determine that the third divided signal and the fourth divided signal are different after the third divided signal and the fourth divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a second discrete output unit of the second safety signal output unit, a second safety signal as one of the plurality of the control signals only when it is determined that the third divided signal and the fourth divided signal are different.
27 more elements
A method of outputting a signal by a signal output apparatus, the method comprising:
- generating, at a signal control unit of the signal output apparatus, two or more control signals based on two or more conditions, which respectively correspond to the two or more control signals;
- and
- outputting, at a signal output unit of the signal output apparatus, a final output signal depending on the two or more control signals and based on an input signal being inputted into the signal output unit;
- wherein the two or more conditions include a first condition and a second condition, and the two or more control signals include a first control signal and a second control signal, and
- wherein the signal control unit includes:
- a first control signal generating unit configured to generate the first control signal in response to the first condition being satisfied among a plurality of conditions;
- a second control signal generating unit configured to generate the second control signal in response to the second condition being satisfied among the plurality of conditions;
- a first control signal dividing unit including:
- a first dividing circuit configured to divide the first control signal into a first divided signal and a second divided signal;
- a first inverter connected to the first dividing circuit;
- and
- a first buffer connected to the first dividing circuit,
- wherein the first divided signal passes through the first inverter and the second divided signal passes through the first buffer;
- a second control signal dividing unit including:
- a second dividing circuit configured to divide the second control signal into a third divided signal and a fourth divided signal;
- a second inverter connected to the second dividing circuit;
- and
- a second buffer connected to the second dividing circuit,
- wherein the third divided signal passes through the second inverter and the fourth divided signal passes through the second buffer;
- a first safety signal output unit configured to:
- compare the first divided signal which is an output of the first inverter and the second divided signal which is an output of the first buffer, the first divided signal and the second divided signal further configured to respectively pass through a first open-collector type inverter component and a second open-collector type inverter component, the first and the second open-collector type inverter components each including at least one inverter;
- determine that the first divided signal and the second divided signal are different after the first divided signal and the second divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a first discrete output unit of the first safety signal output unit, a first safety signal as one of a plurality of the control signals only when it is determined that the first divided signal and the second divided signal are different;
- and
- a second safety signal output unit configured to:
- compare the third divided signal which is an output of the second inverter and the fourth divided signal which is an output of the second buffer, the third divided signal and the fourth divided signal further configured to respectively pass through the first and the second open-collector type inverter components;
- determine that the third divided signal and the fourth divided signal are different after the third divided signal and the fourth divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a second discrete output unit of the second safety signal output unit, a second safety signal as one of the plurality of the control signals only when it is determined that the third divided signal and the fourth divided signal are different.
27 more elements
A non-transitory computer-readable storage medium including computer executable instructions, wherein the instructions, when executed by a processor, cause the processor to:
- generate, at a signal control unit of the processor, two or more control signals based on two or more conditions, which respectively correspond to the two or more control signals;
- and
- output, at a signal output unit of the processor, a final output signal depending on the two or more control signals and based on an input signal being inputted into the signal output unit;
- wherein the two or more conditions include a first condition and a second condition, and the two or more control signals include a first control signal and a second control signal, and
- wherein the signal control unit includes:
- a first control signal generating unit configured to generate the first control signal in response to the first condition being satisfied among a plurality of conditions;
- a second control signal generating unit configured to generate the second control signal in response to the second condition being satisfied among the plurality of conditions;
- a first control signal dividing unit including:
- a first dividing circuit configured to divide the first control signal into a first divided signal and a second divided signal;
- a first inverter connected to the first dividing circuit;
- and
- a first buffer connected to the first dividing circuit,
- wherein the first divided signal is configured to pass through the first inverter and the second divided signal is configured to pass through the first buffer;
- a second control signal dividing unit including:
- a second dividing circuit configured to divide the second control signal into a third divided signal and a fourth divided signal;
- a second inverter connected to the second dividing circuit;
- and
- a second buffer connected to the second dividing circuit,
- wherein the third divided signal is configured to pass through the second inverter and the fourth divided signal is configured to pass through the second buffer;
- a first safety signal output unit configured to:
- compare the first divided signal which is an output of the first inverter and the second divided signal which is an output of the first buffer, the first divided signal and the second divided signal further configured to respectively pass through a first open-collector type inverter component and a second open-collector type inverter component, the first and the second open-collector type inverter components each including at least one inverter;
- determine that the first divided signal and the second divided signal are different after the first divided signal and the second divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a first discrete output unit of the first safety signal output unit, a first safety signal as one of a plurality of the control signals only when it is determined that the first divided signal and the second divided signal are different;
- and
- a second safety signal output unit configured to:
- compare the third divided signal which is an output of the second inverter and the fourth divided signal which is an output of the second buffer, the third divided signal and the fourth divided signal further configured to respectively pass through the first and the second open-collector type inverter components;
- determine that the third divided signal and the fourth divided signal are different after the third divided signal and the fourth divided signal respectively pass through the first and the second open-collector type inverter components;
- and
- output, by a second discrete output unit of the second safety signal output unit, a second safety signal as one of the plurality of the control signals only when it is determined that the third divided signal and the fourth divided signal are different.
27 more elements
Dependencies are inferred from the claim text.