High-bandwidth phase lock loop circuit with sideband rejection

A phase lock loop circuit, comprising:

• a node configured to receive a first signal having a first frequency and a first phase;
• a control circuit, wherein the control circuit is configured to input an estimation having a second frequency and a second phase, wherein the second frequency is selected from a range of frequencies including the first frequency, wherein the range of frequencies is selected so as to exclude sideband signals closest in frequency proximity to the first signal;
• a numerically controlled oscillator coupled to the control circuit, wherein the control circuit is configured to control an output response of the numerically controlled oscillator, wherein the numerically controlled oscillator is configured to:
• receive the estimation from the control circuit, and generate an output signal in response to the estimation;
• and
• a phase detector coupled to the control circuit and the numerically controlled oscillator, wherein the phase detector is configured to:
• compare the first signal and the output signal, and
• produce a comparison output, the comparison output indicative of a phase difference between the first signal and the estimation.

A method comprising:

• receiving a first signal having a first frequency;
• mixing the first signal with a frequency estimation, wherein the frequency estimation is selected from a range of frequencies including the first frequency, wherein the range of frequencies is selected so as to exclude sideband signals closest in frequency proximity to the first signal;
• comparing the first signal and the frequency estimation to determine an error value;
• and
• if the error value is zero, then providing a frequency calculation output in response to the error value.