Systems and methods for rapid processing and storage of data
AssigneeCalifornia Institute of Technology
InventorMark A. Stalzer
Life of this patent
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Abstract
Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.
Claims18
A computing system, comprising:
- a plurality of solid state blades interconnect via a high performance network switch fabric, wherein each solid state blade comprises:
- a processor;
- an array of System on Chip (SOC) computing complexes and associated non-volatile solid state memory components located on the solid state blade;
- wherein the processor is configured to communicate with the array of SOC computing complexes interconnected by an on-blade router;
- wherein each SOC computing complex is directly connected to and communicating with at least one associated and dedicated non-volatile solid state memory component from a plurality of non-volatile solid state memory components located on the solid state blade;
- wherein each SOC computing complex in the array of SOC computing complexes integrates a plurality of functions onto a single chip, the plurality of functions including general processing, accelerated processing, storage control, and communications links, wherein a SOC computing complex integrates on a single chip at least one general processing core, an I/O interface, a cache memory, a memory controller, and a Package on Package DRAM memory;
- wherein the general processing core in a given SOC computing complex is configured to use the memory controller to coordinate reading and writing data to the at least one associated non-volatile solid state memory component within the given SOC computing complex;
- and
- wherein the general processing cores in the plurality of SOC computing complexes are configured to directly read from and write data to the non-volatile solid state memory component to which they are connected in parallel.
Dependencies are inferred from the claim text.