Information processing apparatus stopping power supply to hardware connected to a socket
AssigneeCanon Kabushiki Kaisha
InventorXiaoli Wang
Life of this patent
Estimating the term…
Abstract
The present invention provides an information processing apparatus capable of mounting an optional hardware. The information processing apparatus comprises a processor, an image processing circuit and a socket to which the optional hardware is to be mounted, wherein the optional hardware being connected to the socket communicates with the image processing circuit. The processor transmits a predetermined packet to the optional hardware mounted to the socket, receive a response packet to the predetermined packet from the image processing circuit, determines whether or not the received response packet is an expected response packet, and controls supplying power to the optional hardware in accordance with a determination result of the received response packet.
Claims16
An information processing apparatus capable connecting a hardware, the information processing apparatus comprising:
- a plurality of processing circuits or processors;
- a socket to which the hardware is to be connected, wherein the hardware being connected to the socket and the plurality of processing circuits or processors are connected in series via a bus;
- a power source that supplies power to the plurality of processing circuits or processors and the hardware being connected to the socket,
- wherein one of the plurality of processing circuits or processors:
- transmit a predetermined packet to the bus;
- receive a response packet to the predetermined packet;
- determine whether or not the received response packet is an expected response packet;
- and
- control stopping power supply from the power source to the hardware being connected to the socket and the plurality of processing circuits or processors connected via the bus based on a determination result of the received response packet,
- wherein the predetermined packet includes additional information encrypted on a basis of a date and time and model information of the information processing apparatus, and the expected response packet includes information obtained by decrypting the additional information.
A method of controlling an information processing apparatus including a plurality of processing circuits or processors, and a socket to which a hardware is to be connected, wherein the hardware being connected to the socket and the plurality of processing circuits or processors are connected in series via a bus, and a power source that supplied power to the plurality of processing circuits or processors and the hardware being connected to the socket, the method comprising:
- one of the plurality of processing circuits or processors performs:
- transmitting a predetermined packet to the bus;
- receiving a response packet to the predetermined packet;
- determining whether or not the response packet is an expected response packet;
- and
- controlling supplying power from the power source to the hardware being connected to the socket and the plurality of processing circuits or processors connected via the bus based on a determination result in the determining,
- wherein the predetermined packet includes additional information encrypted on a basis of a date and time and model information of the information processing apparatus, and the expected response packet includes information obtained by decrypting the additional information.
An information processing apparatus, comprising:
- a plurality of processing circuits or processors;
- a socket that is capable of connecting a hardware, wherein the hardware being connected to the socket and the plurality of processing circuits or processors are connected in series via a bus;
- and
- a power source that supplied power to the plurality of processing circuits or processors and the hardware being connected to the socket,
- wherein one of the plurality of processing circuits or processors transmits a predetermined packet to the bus,
- upon receiving a response packet to the predetermined packet, the one of the plurality of processing circuits or processors determines whether or not the response packet is an expected response packet, and
- the one of the plurality of processing circuits or processors controls supplying power from the power source to the hardware being connected to the socket and the plurality of processing circuits or processors connected via the bus based on a determination result of the response packet,
- wherein the predetermined packet includes additional information encrypted on a basis of a date and time and model information of the information processing apparatus, and the expected response packet includes information obtained by decrypting the additional information.
Dependencies are inferred from the claim text.