Second-order ΔΣ modulator, radio, and signal processing method performed by second-order ΔΣ modulator
AssigneeNEC Corporation
InventorMasaaki Tanio
Life of this patent
Estimating the term…
Abstract
A second-order ΔΣ modulator includes: a two-stage integrator; a first arithmetic operation circuit; and a second arithmetic operation circuit. The two-stage integrator includes a plurality of adder arrays, each of which includes a plurality of adders. The plurality of adder arrays includes first to fourth adder arrays. An output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array. An output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array. A sum bit string obtained in the first adder array is input to the third adder array. A sum bit string obtained in the second adder array is input to the fourth adder array.
Claims7
A second-order ΔΣ (delta sigma) modulator comprising:
- a two-stage integrator;
- a first arithmetic operation circuit;
- and
- a second arithmetic operation circuit,
- wherein the two-stage integrator comprises a plurality of adder arrays, each of the plurality of adder arrays comprises a plurality of adders,
- the plurality of adder arrays comprises a first adder array, a second adder array, a third adder array, and a fourth adder array,
- an output of a last stage of the second adder array is fed back as an input of a first stage of the first adder array,
- an output of a last stage of the fourth adder array is fed back as an input of a first stage of the third adder array,
- a sum bit string obtained in the first adder array is input to the third adder array,
- a sum bit string obtained in the second adder array is input to the fourth adder array,
- the first arithmetic operation circuit performs an arithmetic operation based on inputs supplied to the plurality of adders of the first adder array, and inputs an arithmetic operation result to the second adder array, and
- the second arithmetic operation circuit performs an arithmetic operation based on the inputs supplied to the plurality of adders of the first adder array and inputs supplied to the plurality of adders of the third adder array, and inputs an arithmetic operation result to the fourth adder array.
A signal processing method performed by a second-order ΔΣ (delta sigma) modulator, the second-order ΔΣ modulator comprising a two-stage integrator, a first arithmetic operation circuit, and a second arithmetic operation circuit, the two-stage integrator comprising a plurality of adder arrays that comprise a first adder array, a second adder array, a third adder array, and a fourth adder array, each of the plurality of adder arrays comprising a plurality of adders, the method comprising:
- feeding back an output of a last stage of the second adder array as an input of a first stage of the first adder array;
- feeding back an output of a last stage of the fourth adder as an input of a first stage of the third adder array;
- inputting a sum bit string obtained in the first adder array to the third adder array;
- inputting a sum bit string obtained in the second adder array to the fourth adder array;
- performing an arithmetic operation based on inputs supplied to the plurality of adders of the first adder array to input an arithmetic operation result to the second adder array, by the first arithmetic operation circuit;
- and
- performing an arithmetic operation based on the inputs supplied to the plurality of adders of the first adder array and inputs supplied to the plurality of adders of the third adder array to input an arithmetic operation result to the fourth adder array, by the second arithmetic operation circuit.
Dependencies are inferred from the claim text.