Discrete time charge sharing IIR bandpass filter incorporating clock phase reuse

A discrete time bandpass filter, comprising:

• a quadrature input node for receiving a complex input signal;
• a plurality of first switched history capacitors (CH1 ), each first switched history capacitor associated with a different element of said quadrature input node;
• a sharing capacitor (CS) coupled to said plurality of first switched history capacitors and operative to cyclically share charge therewith;
• a plurality of capacitor arrays, each output capacitor array coupled to a respective first switched history capacitor and including one or more second switched history capacitors;
• a clock generator operative to generate a plurality of clock phases;
• wherein during each multi-phase cycle of said filter:
• a single first switched history capacitor is connected to said sharing capacitor;
• charge is shared from at least one second switched history capacitor to a neighboring second switched history capacitor in each capacitor array;
• multiple second switched history capacitors in said plurality of output capacitor arrays share the same clock phase;
• and
• wherein charge is shared between neighboring second switched history capacitors within each capacitor array in a predetermined sequence to generate a quadrature output thereby.

A discrete time bandpass filter method, the method comprising:

• receiving a complex input signal at a quadrature input node;
• providing a plurality of first switched history capacitors (CH1), each first switched history capacitor associated with a different element of said quadrature input node;
• cyclically sharing charge between a sharing capacitor (CS) and said plurality of first switched history capacitors;
• providing a plurality of capacitor arrays, each output capacitor array coupled to a respective first switched history capacitor and including one or more second switched history capacitors;
• generating a plurality of clock phases;
• wherein during each multi-phase cycle of said filter:
• connecting one of said first switched history capacitors to said sharing capacitor;
• sharing charge between at least one second switched history capacitor and a neighboring second switched history capacitor in each capacitor array;
• reusing each clock phase one or more times, multiple second switched history capacitors in said plurality of output capacitor arrays sharing the same clock phase;
• and
• sharing charge between neighboring second switched history capacitors within each capacitor array in a predetermined sequence to generate a quadrature output thereby.