Integrated circuit including asymmetric ending cells and system-on-chip including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-kyu Ryu, Min-su Kim, Dae-seong Lee
Life of this patent
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Abstract
An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.
Claims20
An integrated circuit comprising:
- first and second macroblocks arranged in a first direction;
- and
- a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including,
- first ending cells adjacent to the first macroblock, the first ending cells concatenated in a line in a second direction perpendicular to the first direction, each of the first ending cells having a first width in the first direction,
- second ending cells adjacent to the second macroblock, the second ending cells concatenated in a line in the second direction, each of the second ending cells having the first width in the first direction, and
- center cells concatenated in a line in the second direction in an area between the first ending cells and the second ending cells.
A system-on-chip comprising:
- an application processor including,
- first and second macroblocks arranged in a first direction, and
- a plurality of cells between the first and second macroblocks, the plurality of cells having,
- first ending cells adjacent to the first macroblock and concatenated in a line in a second direction perpendicular to the first direction, each of the first ending cells having a first width in the first direction, the second direction being perpendicular to the first direction,
- second ending cells adjacent to the second macroblock and concatenated in a line in the second direction, each of the second ending cells having a second width in the first direction, the second width being different from the first width, each of the second ending cells being asymmetrical to each of the first ending cells, and
- at least one standard cell between the first ending cells and the second ending cells;
- and
- a memory electrically connected to the application processor.
An integrated circuit comprising:
- first and second macroblocks arranged in a first direction;
- and
- a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including,
- at least one first ending cell adjacent to the first macroblock, the first ending cells concatenated in a line in a second direction perpendicular to the first direction, the at least one first ending cell having a first width in the first direction,
- at least one second ending cell adjacent to the second macroblock, the second ending cells concatenated in a line in the second direction, the at least one second ending cell having a second width different from the first width in the first direction, and
- a plurality of standard cells between the at least one first ending cell and the at least one second ending cell,
- wherein only one of the at least one first ending cell and the at least one second ending cell comprises a tap configured to receive a power supply voltage or a ground voltage and provide the power supply voltage or the ground voltage to an active region.
Dependencies are inferred from the claim text.